Datasheet

Rev. 0 | Page 34 of 44 | March 2006
ADSP-21261
SPI Protocol—Master
SPI Protocol—Slave
See Table 30 and Figure 26.
Table 29. SPI Protocol—Master
Parameter Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid to SPICLK Edge (Data Input Setup Time) 5 ns
t
HSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid 2 ns
Switching Characteristics
t
SPICLKM
Serial Clock Cycle 8 × t
CCLK
ns
t
SPICHM
Serial Clock High Period 4 × t
CCLK
– 2 ns
t
SPICLM
Serial Clock Low Period 4 × t
CCLK
– 2 ns
t
DDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time) 3 ns
t
HDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 10 ns
t
SDSCIM
FLAG3–0 OUT (SPI Device Select) Low to First SPICLK Edge 4 × t
CCLK
– 2 ns
t
HDSM
Last SPICLK Edge to FLAG3–0 OUT High 4 × t
CCLK
– 1 ns
t
SPITDM
Sequential Transfer Delay 4 × t
CCLK
– 1 ns
Figure 25. SPI Protocol—Master
LSB
VALID
MSB
VALID
t
SSPIDM
t
HSPIDM
t
HDSPIDM
LSBMSB
t
HSPIDM
t
DDSPIDM
MOSI
(OUTPUT)
MISO
(INPUT)
FLAG3–0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
t
SPICHM
t
SPICLM
t
SPICLM
t
SPICLKM
t
SPICHM
t
HDSM
t
SPITDM
t
HDSPIDM
LSB
VALID
LSBMSB
MSB
VALID
t
HSPIDM
t
DDSPIDM
MOSI
(OUTPUT)
MISO
(INPUT)
t
SSPIDM
CPHASE = 1
CPHASE = 0
t
SDSCIM
t
SSPID M