Datasheet

ADSP-21261
Rev. 0 | Page 31 of 44 | March 2006
Figure 22. Serial Ports
DRIVE EDGE
DAI_P20–1
SCLK (INT)
DRIVE EDGE DRIVE E DGE
SCLK
DAI_P20–1
SCLK (EXT)
t
DDTTE
t
DDTEN
t
DDTIN
DAI_P20–1
(DATA CHANNEL A/B)
DAI_P20–1
(DATA CHANNEL A/B)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DRIVE EDGE SAMPLE EDGE
DATA R
E
C
E
IV
E
—INT
E
RNAL CLOCK DATA R
E
C
E
IV
E
—
E
X
T
E
RNAL CLOCK
DRIVE EDGE SAMPLE EDGE
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
SDRI
t
HDRI
t
SFSI
t
HFSI
t
DFSI
t
HOFSI
t
SCLKIW
t
SDRE
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKW
t
HOFSE
DAI_P20–1
(DATA CHANNEL A/B)
t
DDTI
DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT—INTERNAL CLOCK
t
SFSI
t
HFSI
t
DFSI
t
HOFSI
t
SCLKIW
t
HDTI
NOTE: EITHER THE RISING EDGE OR FALLING EDGE O F SCLK (EXTERNAL) OR SCLK (INTERNAL) CAN BE USED AS THE ACTIVE SAMPLING EDGE.
t
DDTE
DRIVE EDGE SAMPLE EDGE
DATA TRANSMIT—EXTERNAL CLOCK
t
SFSE
t
HFSE
t
DFSE
t
HOFSE
t
SCLKW
t
HDTE
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL A/B)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL A/B)
DAI_P20–1
(SCLK)
DAI_P20–1
(FS)
DAI_P20–1
(DATA CHANNEL A/B)