Datasheet

Rev. 0 | Page 30 of 44 | March 2006
ADSP-21261
Table 25. Serial Ports—Enable and Three-State
Parameter Min Max Unit
Switching Characteristics
t
DDTEN
Data Enable from External Transmit SCLK
1
2ns
t
DDTTE
Data Disable from External Transmit SCLK
1
7ns
t
DDTIN
Data Enable from Internal Transmit SCLK
1
–1 ns
1
Referenced to drive edge.
Table 26. Serial Ports—External Late Frame Sync
Parameter Min Max Unit
Switching Characteristics
t
DDTLFSE
Data Delay from Late External Transmit FS or External Receive FS
with MCE = 1, MFD = 0
1
7ns
t
DDTENFS
Data Enable for MCE = 1, MFD = 0
1
0.5 ns
1
The t
DDTLFSE
and t
DDTENFS
parameters apply to left-justified sample pair mode as well as DSP serial mode, and MCE = 1, MFD = 0.
Figure 21. External Late Frame Sync
1
1
This figure reflects changes made to support left-justified sample pair mode.
DRIVE SAMPLE DRIVE
DAI_P20–1
(SCLK)
DAI_P20– 1
(FS)
DAI_P20–1
(DATA CHANNEL A/B)
DRIVE SAMPLE DRIVE
LATE EXTERNAL TRANSMIT FS
EXTERNAL RECEIVE FS WITH MCE = 1, MFD = 0
1ST BIT 2ND BIT
DAI_P20– 1
(SCLK)
DAI_P20–1
(FS)
1ST BIT 2ND BIT
t
HFSE/I
t
SFSE/I
t
DDTE/I
t
DDTENFS
t
DDTLFSE
t
HDTE/I
t
SFSE/I
t
DDTE/I
t
DDTENFS
t
DDTLFSE
t
HDTE/I
DAI_P 20–1
(DATA CHANNEL A/B)
NOTE: SERIAL PORT SIGNALS (SCLK, FS, DATA CHANNEL A/B) ARE ROUTED TO THE DAI_P[20:1] PINS
USING THE SRU. THE TIMING SPECIFICATIONS PROVIDED HERE ARE VALID AT THE DAI_P[20:1] PINS.
t
HFSE/I