Datasheet

ADSP-21261
Rev. 0 | Page 27 of 44 | March 2006
Memory Write—Parallel Port
Use the specifications in Table 21, Table 22, Figure 19, and
Figure 20 for asynchronous interfacing to memories (and
memory-mapped peripherals) when the ADSP-21261 is access-
ing external memory space.
Table 21. 8-Bit Memory Write Cycle
Parameter Min Max Unit
Switching Characteristics
t
ALEW
ALE Pulse Width 2 × t
CCLK
– 2 ns
t
ALERW
ALE Deasserted to Read/Write Asserted 1 × t
CCLK
– 0.5 ns
t
ADAS
Address/Data15–0 Setup Before ALE Deasserted
1
2.5 × t
CCLK
– 2.0 ns
t
ADAH
Address/Data15–0 Hold After ALE Deasserted
1
0.5 × t
CCLK
– 0.8 ns
t
WW
WR Pulse Width D – 2 ns
t
ADWL
Address/Data15–8 to WR Low 0.5 × t
CCLK
– 1.5 ns
t
ADWH
Address/Data15–8 Hold After WR High 0.5 × t
CCLK
– 1 + H ns
t
ALEHZ
ALE Deasserted
1
to Address/Data15–0 in High Z 0.5 × t
CCLK
– 0.8 0.5t
CCLK
+ 2.0 ns
t
DWS
Address/Data7–0 Setup Before WR High D ns
t
DWH
Address/Data7–0 Hold After WR High 0.5 × t
CCLK
– 1.5 + H ns
t
DAWH
Address/Data to WR High D ns
D = (data cycle duration) × t
CCLK
H = t
CCLK
(if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Figure 19. 8-Bit Memory Write Cycle
AD15–8
VALID ADDRESS VALID ADDRESS
t
ADAS
AD7–0
t
ALEW
ALE
RD
t
WW
WR
t
ADAH
t
ADWH
t
ADWL
t
ALEHZ
VALID DATA
t
DWS
t
DWH
VALID ADDRESS
t
DAWH
t
ALERW