Datasheet

Rev. 0 | Page 26 of 44 | March 2006
ADSP-21261
Table 20. 16-Bit Memory Read Cycle
Parameter Min Max Unit
Timing Requirements
t
DRS
Address/Data15–0 Setup Before RD high 3.3 ns
t
DRH
Address/Data15–0 Hold After RD high 0 ns
Switching Characteristics
t
ALEW
ALE Pulse Width 2 × t
CCLK
– 2 ns
t
ALERW
ALE Deasserted to Read/Write Asserted 1 × t
CCLK
– 0.5 ns
t
ADAS
Address/Data15–0 Setup Before ALE Deasserted
1
2.5 × t
CCLK
– 2.0 ns
t
ADAH
Address/Data15–0 Hold After ALE Deaserted
1
0.5 × t
CCLK
– 0.8 ns
t
ALEHZ
ALE Deasserted
1
to Address/Data15–0 in High Z 0.5 × t
CCLK
– 0.8 0.5t
CCLK
+ 2.0 ns
t
RW
RD Pulse Width D – 2 ns
D = (data cycle duration) × t
CCLK
H = t
CCLK
(if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Figure 18. 16-Bit Memory Read Cycle
VALID ADDRESS
VALID DATA
t
ADAS
t
ADAH
AD15–0
t
ALEHZ
t
DRS
t
DRH
t
ALEW
ALE
RD
t
RW
WR
t
ALERW