Datasheet

ADSP-21261
Rev. 0 | Page 25 of 44 | March 2006
Memory Read—Parallel Port
The specifications in Table 19, Table 20, Figure 17, and
Figure 18 are for asynchronous interfacing to memories (and
memory-mapped peripherals) when the ADSP-21261 is access-
ing external memory space.
Table 19. 8-Bit Memory Read Cycle
Parameter Min Max Unit
Timing Requirements
t
DRS
Address/Data7–0 Setup Before RD High 3.3 ns
t
DRH
Address/Data7–0 Hold After RD High 0 ns
t
DAD
Address 15–8 to Data Valid D + 0.5 × t
CCLK
– 3.5 ns
Switching Characteristics
t
ALEW
ALE Pulse Width 2 × t
CCLK
– 2 ns
t
ALERW
ALE Deasserted to Read/Write Asserted 1 × t
CCLK
– 0.5 ns
t
ADAS
Address/Data15–0 Setup Before ALE Deasserted
1
2.5 × t
CCLK
– 2.0 ns
t
ADAH
Address/Data15–0 Hold After ALE Deasserted
1
0.5 × t
CCLK
– 0.8 ns
t
ALEHZ
ALE Deasserted
1
to Address/Data7–0 in High Z 0.5 × t
CCLK
– 0.8 0.5 × t
CCLK
+ 2.0 ns
t
RW
RD Pulse Width D – 2 ns
t
ADRH
Address/Data15–8 Hold After RD High 0.5 × t
CCLK
– 1 + H ns
D = (data cycle duration) × t
CCLK
H = t
CCLK
(if a hold cycle is specified, else H = 0)
1
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
Figure 17. 8-Bit Memory Read Cycle
VALID DATA
AD15–8
VALID ADDRES S VALID ADDRESS
t
ADAS
VALID ADDRESS
AD7–0
t
ALEW
ALE
RD
t
RW
WR
t
ADAH
t
ADRH
t
ALEHZ
t
DRS
t
DRH
t
DAD
t
ALERW