Datasheet

ADSP-21261
Rev. 0 | Page 21 of 44 | March 2006
Timer PWM_OUT Cycle Timing
The timing specification in Table 14 and Figure 12 applies to
Timer PWM_OUT (pulse-width modulation) mode. Timer sig-
nals are routed to the DAI_P20–1 pins through the SRU.
Therefore, the timing specifications provided below are valid at
the DAI_P20–1 pins.
Timer WDTH_CAP Timing
The timing specification in Table 15 and Figure 13 applies to
Timer WDTH_CAP (pulse width count and capture) mode.
Timer signals are routed to the DAI_P20–1 pins through the
SRU. Therefore, the timing specifications provided below are
valid at the DAI_P20–1 pins.
Table 14. Timer PWM_OUT Timing
Parameter Min Max Unit
Switching Characteristic
t
PWMO
Timer Pulse Width Output 2 t
CCLK
– 1 2(2
31
– 1) t
CCLK
ns
Figure 12. Timer PWM_OUT Timing
DAI_P20– 1
(TIMER)
t
PWMO
Table 15. Timer Width Capture Timing
Parameter Min Max Unit
Timing Requirement
t
PWI
Timer Pulse Width 2 t
CCLK
2(2
31
– 1) t
CCLK
ns
Figure 13. Timer Width Capture Timing
DAI_P20–1
(TIMER)
t
PWI