Datasheet

Rev. 0 | Page 20 of 44 | March 2006
ADSP-21261
Reset
See Table 11 and Figure 9.
Interrupts
The timing specification in Table 12 and Figure 10 applies to the
FLAG0, FLAG1, and FLAG2 pins when they are configured as
IRQ0
, IRQ1, and IRQ2 interrupts. Also applies to DAI_P20–1
pins when configured as interrupts.
Core Timer
The timing specification in Table 13 and Figure 11 applies to
FLAG3 when it is configured as the core timer (CTIMER).
Table 11. Reset
Parameter Min Max Unit
Timing Requirements
t
WRST
RESET Pulse Width Low
1
4t
CK
ns
t
SRST
RESET Setup Before CLKIN Low 8 ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 μs while RESET is low, assuming
stable VDD and CLKIN (not including start-up time of external clock oscillator).
Figure 9. Reset
CLKIN
RESET
t
WRST
t
SRST
Table 12. Interrupts
Parameter Min Max Unit
Timing Requirement
t
IPW
IRQx Pulse Width 2 × t
CCLK
+2 ns
Figure 10. Interrupts
DAI_P20–1
(FLAG2–0 )
(IRQ2–0)
t
IPW
Table 13. Core Timer
Parameter Min Max Unit
Switching Characteristic
t
WCTIM
CTIMER Pulse Width 4 × t
CCLK
– 1 ns
Figure 11. Core Timer
FLAG3
(CTIMER)
t
WCTIM