Datasheet

ADSP-21261
Rev. 0 | Page 19 of 44 | March 2006
Clock Input
See Table 10 and Figure 7.
Clock Signals
The ADSP-21261 can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21261 to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL. Figure 8 shows
the component connections used for a crystal operating in fun-
damental mode. Note that the 150 MHz clock rate is achieved
using a 9.375 MHz crystal and a PLL multiplier ratio 16:1
(CCLK:CLKIN).
Table 10. Clock Input
Parameter Min Max Unit
Timing Requirements
t
CK
CLKIN Period 20
1
160
2
ns
t
CKL
CLKIN Width Low 7.5
1
80
2
ns
t
CKH
CLKIN Width High 7.5
1
80
2
ns
t
CKRF
CLKIN Rise/Fall (0.4 V–2.0 V) 3 ns
t
CCLK
CCLK Period
3
6.66 10 ns
1
Applies only for CLKCFG1–0 = 00 and default values for PLL control bits in PMCTL.
2
Applies only for CLKCFG1–0 = 01 and default values for PLL control bits in PMCTL.
3
Any changes to PLL control bits in the PMCTL register must meet core clock timing specification t
CCLK
.
Figure 7. Clock Input
Figure 8. 150 MHz Operation with a 9.375 MHz
Fundamental Mode Crystal
CLKIN
t
CK
t
CKH
t
CKL
CLKIN XTAL
C1 C2
X1
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. CRYSTAL
SELECTION MUST COMPLY WITH CLKCFG1–0 = 10 OR = 01.
1M⍀