Datasheet

Rev. 0 | Page 14 of 44 | March 2006
ADSP-21261
ADDRESS DATA PINS AS FLAGS
To use these pins as flags (FLAG15–0) set (=1) Bit 20 of the
SYSCTL register and disable the parallel port.
BOOT MODES
CORE INSTRUCTION RATE TO CLKIN RATIO MODES
ADDRESS DATA MODES
Table 6 shows the functionality of the AD pins for 8-bit and
16-bit transfers to the parallel port. For 8-bit data transfers, ALE
latches address bits A23–A8 when asserted, followed by address
bits A7–A0 and data bits D7–D0 when deasserted. For 16-bit
data transfers, ALE latches address bits A15–A0 when asserted,
followed by data bits D15–D0 when deasserted.
Table 3. AD15–0 to FLAG Pin Mapping
AD Pin Flag Pin
AD0 FLAG8
AD1 FLAG9
AD2 FLAG10
AD3 FLAG11
AD4 FLAG12
AD5 FLAG13
AD6 FLAG14
AD7 FLAG15
AD8 FLAG0
AD9 FLAG1
AD10 FLAG2
AD11 FLAG3
AD12 FLAG4
AD13 FLAG5
AD14 FLAG6
AD15 FLAG7
Table 4. Boot Mode Selection
BOOTCFG1–0 Booting Mode
00 SPI Slave Boot
01 SPI Master Boot
10 Parallel Port Boot via EPROM
11 Internal Boot Mode (ROM code only)
Table 5. Core Instruction Rate/CLKIN Ratio Selection
CLKCFG1–0 Core to CLKIN Ratio
00 3:1
01 16:1
10 8:1
11 Reserved
Table 6. Address/Data Mode Selection
EP Data
Mode ALE
AD7–0
Function
AD15–8
Function
8-bit Asserted A15–8 A23–16
8-bit Deasserted D7–0 A7–0
16-bit Asserted A7–0 A15–8
16-bit Deasserted D7–0 D15–8