Datasheet

Rev. C | Page 8 of 60 | January 2013
ADSP-21161N
setup and message registers. DMA setup via a host would allow
it to access any internal memory address via DMA transfers.
Vector interrupt support provides efficient execution of host
commands.
The host processor interface can be used in either multiproces-
sor or single processor SHARC systems. For multiprocessor
systems, host access to the SHARC requires address pins
ADDR17, ADDR18, ADDR19, and ADDR20 to be driven low.
It is not enough to tie these pins to ground through a resistor
Figure 5. Shared Memory Multiprocessing System
ACK
OE
ADDR
DATA
CS
WE
GLOBAL
MEMORY
AND
PERIPHERALS
(OPTIONAL)
C
O
N
T
R
O
L
ADSP-21161N #1
ADDR23-0
CONTROL
ADSP-21161N #3
ID2-0
RESET
CLKIN
3
ADSP-21161N #4
CLOCK
ADDR
DATA
SDRAM
(OPTIONAL)
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
ID2-0
RESET
CLKIN
C
O
N
T
R
O
L
A
D
D
R
E
S
S
D
A
T
A
C
O
N
T
R
O
L
A
D
D
R
E
S
S
D
A
T
A
CONTROL
ADSP-21161N #2
ID2-0
RESET
CLKIN
2
1
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
WE
RAS
CAS
DQM
CLK
A10
CKE
CS
DATA47-16
SDWE
RAS
CAS
DQM
SDCLK1-0
SDA10
SDCKE
BR6-2
RD
MS3-0
SBTS
CS
ACK
BR1
REDY
HBG
HBR
WR
BMS
ADDR23-0
RESET
DATA47-16
ADDR23-0
DATA47-16