Datasheet

Rev. C | Page 50 of 60 | January 2013
ADSP-21161N
SPI Interface Specifications
Table 36. SPI Interface Protocol — Master Switching and Timing
100 MHz 110 MHz
UnitParameter Min Max Min Max
Timing Requirements
t
SSPIDM
Data Input Valid to SPICLK Edge (Data Input Set-up Time) 0.5t
CCLK
+10 0.5t
CCLK
+10 ns
t
HSPIDM
SPICLK Last Sampling Edge to Data Input Not Valid 0.5t
CCLK
+1 0.5t
CCLK
+1 ns
Switching Characteristics
t
SPICLKM
Serial Clock Cycle 8t
CCLK
8t
CCLK
–4 ns
t
SPICHM
Serial Clock High Period 4t
CCLK
–4 4t
CCLK
–4 ns
t
SPICLM
Serial Clock Low Period 4t
CCLK
–4 4t
CCLK
–4 ns
t
DDSPIDM
SPICLK Edge to Data Out Valid (Data Out Delay Time) 3 3 ns
t
HDSPIDM
SPICLK Edge to Data Out Not Valid (Data Out Hold Time) 0 0 ns
t
SDSCIM_0
FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for
CPHASE = 0
5t
CCLK
5t
CCLK
ns
t
SDSCIM_1
FLAG3–0 (SPI Device Select) Low to First SPICLK Edge for
CPHASE = 1
3t
CCLK
3t
CCLK
ns
t
HDSM
Last SPICLK Edge to FLAG3–0 High t
CCLK
–3 t
CCLK
–3 ns
t
SPITDM
Sequential Transfer Delay 2t
CCLK
2t
CCLK
ns
Figure 31. SPI Interface Protocol — Master Switching and Timing
LSB
VALID
MSB
VALID
t
SSPIDM
t
H S PIDM
t
HDSPIDM
LSBMSB
t
H S PIDM
t
DDSPIDM
MOSI
(OUTPUT)
MISO
(INPUT)
FLAG3-0
(OUTPUT)
SPICLK
(CP = 0)
(OUTPUT)
SPICLK
(CP = 1)
(OUTPUT)
t
S PICHM
t
S PICLM
t
S PICLM
t
S PICLKM
t
S PICHM
t
HDS M
t
S PITDM
t
HDS PIDM
LSB
VALID
LSBMSB
MSB
VALID
t
H S PIDM
t
DDS PIDM
MOSI
(OUTPUT)
MISO
(INPUT)
t
SSPIDM
CPHASE=1
CPHASE=0
t
S D S CIM
t
SSPIDM