Datasheet

Rev. C | Page 46 of 60 | January 2013
ADSP-21161N
Serial Ports
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 30. Serial Ports — External Clock
Parameter Min Max Unit
Timing Requirements
t
SFSE
Transmit/Receive FS Setup Before Transmit/Receive SCLK
1
3.5 ns
t
HFSE
Transmit/Receive FS Hold After Transmit/Receive SCLK
1
2ns
t
SDRE
Receive Data Setup Before Receive SCLK
1
1.5 ns
t
HDRE
Receive Data Hold After Receive SCLK
1
4ns
t
SCLKW
SCLKx Width 7 ns
t
SCLK
SCLKx Period 2t
CCLK
ns
1
Referenced to sample edge.
Table 31. Serial Ports — Internal Clock
Parameter Min Max Unit
Timing Requirements
t
SFSI
FS Setup Time Before SCLK (Transmit/Receive Mode)
1
8ns
t
HFSI
FS Hold After SCLK (Transmit/Receive Mode)
1
0.5t
CCLK
+1 ns
t
SDRI
Receive Data Setup Before SCLK
1
4ns
t
HDRI
Receive Data Hold After SCLK
1
3ns
1
Referenced to sample edge.
Table 32. Serial Ports — External Clock
Parameter
100 MHz 110 MHz
UnitMin Max Min Max
Switching Characteristics
t
DFSE
FS Delay After SCLK (Internally Generated FS)
1, 2, 3
13 13 ns
t
HOFSE
FS Hold After SCLK (Internally Generated FS)
1, 2 , 3
32.75ns
t
DDTE
Transmit Data Delay After SCLK
1, 2
16 16 ns
t
HDTE
Transmit Data Hold After SCLK
1, 2
00ns
1
Referenced to drive edge.
2
SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
3
SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.
Table 33. Serial Ports — Internal Clock
Parameter Min Max Unit
Switching Characteristics
t
DFSI
FS Delay After SCLK (Internally Generated FS)
1, 2, 3
4.5 ns
t
HOFSI
FS Hold After SCLK (Internally Generated FS)
1, 2, 3
–1.5 ns
t
DDTI
Transmit Data Delay After SCLK
1, 2
7.5 ns
t
HDTI
Transmit Data Hold After SCLK
1, 2
0ns
t
SCLKIW
SCLK Width
2
0.5t
SCLK
–2.5 0.5t
SCLK
+2 ns
1
Referenced to drive edge.
2
SCLK/FS Configured as a transmit clock/frame sync with the DDIR bit = 1 in SPCTLx register.
3
SCLK/FS Configured as a receive clock/frame sync with the DDIR bit = 0 in SPCTLx register.