Datasheet

ADSP-21161N
Rev. C | Page 45 of 60 | January 2013
Table 29. Link Ports — Transmit
Parameter Min Max Unit
Timing Requirements
t
SLACH
LACK Setup Before LCLK High 8 ns
t
HLACH
LACK Hold After LCLK High –2 ns
Switching Characteristics
t
DLDCH
Data Delay After LCLK High 3 ns
t
HLDCH
Data Hold After LCLK High 0 ns
t
LCLKTWL
LCLK Width Low 0.5t
LCLK
–1.0 0.5t
LCLK
+1.0 ns
t
LCLKTWH
LCLK Width High 0.5t
LCLK
–1.0 0.5t
LCLK
+1.0 ns
t
DLACLK
LCLK Low Delay After LACK High 0.5t
LCLK
+3 3t
LCLK
+11 ns
Figure 28. Link Ports—Transmit
LCLK
LDAT7-0
LACK (IN)
THE
t
SLACH
REQUIREMENT APPLIES TO THE RISING EDGE OF LCLK ONLY FOR THE FIRST NIBBLE TRANSMITTED.
TRANSMIT
LAST NIBBLE/BYTE
TRANSMITTED
FIRST NIBBLE/BYTE
TRANSMITTED
LCLK INACTIVE
(HIGH)
OUT
t
DLDCH
t
HLDCH
t
LCLKTWH
t
LCLKTWL
t
SLACH
t
HLACH
t
DLACLK