Datasheet

Rev. C | Page 44 of 60 | January 2013
ADSP-21161N
Link Ports
Calculation of link receiver data setup and hold relative to link
clock is required to determine the maximum allowable skew
that can be introduced in the transmission path between
LDATA and LCLK. Setup skew is the maximum delay that can
be introduced in LDATA relative to LCLK,
(setup skew = t
LCLKTWH
min – t
DLDCH
– t
SLDCL
). Hold skew is the
maximum delay that can be introduced in LCLK relative to
LDATA, (hold skew = t
LCLKTWL
min – t
HLDCH
– t
HLDCL
). Calcula-
tions made directly from speed specifications will result in
unrealistically small skew times because they include multiple
tester guardbands. The setup and hold skew times shown below
are calculated to include only one tester guardband.
ADSP-21161N Setup Skew = 1.5 ns max
ADSP-21161N Hold Skew = 1.5 ns max
Note that there is a two-cycle effect latency between the link
port enable instruction and the DSP enabling the link port.
Table 28. Link Ports — Receive
Parameter Min Max Unit
Timing Requirements
t
SLDCL
Data Setup Before LCLK Low 1 ns
t
HLDCL
Data Hold After LCLK Low 3.5 ns
t
LCLKIW
LCLK Period t
LCLK
ns
t
LCLKRWL
LCLK Width Low 4.0 ns
t
LCLKRWH
LCLK Width High 4.0 ns
Switching Characteristics
t
DLALC
LACK Low Delay After LCLK High
1
812ns
1
LACK goes low with t
DLALC
relative to rise of LCLK after first nibble, but does not go low if the receiver's link buffer is not about to fill.
Figure 27. Link Ports—Receive
LCLK
LDAT7-0
LACK (OUT)
RECEIVE
IN
t
SLDCL
t
HLDCL
t
DLALC
t
LCLKRWL
t
LCLKIW
t
LCLKRW H