Datasheet

Rev. C | Page 42 of 60 | January 2013
ADSP-21161N
SDRAM Interface — Bus Master
Use these specifications for ADSP-21161N bus master accesses
of SDRAM:
SDRAM Interface — Bus Slave
These timing requirements allow a bus slave to sample the bus
master’s SDRAM command and detect when a refresh occurs:
Table 26. SDRAM Interface — Bus Master
Parameter
100 MHz 110 MHz
UnitMin Max Min Max
Timing Requirements
t
SDSDK
Data Setup Before SDCLK 2.0 2.0 ns
t
HDSDK
Data Hold After SDCLK 2.3 2.3 ns
Switching Characteristics
t
DSDK1
First SDCLK Rise Delay After CLKIN
1, 2
0.75t
CCLK
+ 1.5 0.75t
CCLK
+ 8.0 0.75t
CCLK
+ 1.5 0.75t
CCLK
+ 8.0 ns
t
SDK
SDCLK Period t
CCLK
2  t
CCLK
t
CCLK
2  t
CCLK
ns
t
SDKH
SDCLK Width High 4 3 ns
t
SDKL
SDCLK Width Low 4 3 ns
t
DCADSDK
Command, Address, Data, Delay After SDCLK
3
0.25t
CCLK
+2.5 0.25t
CCLK
+2.5 ns
t
HCADSDK
Command, Address, Data, Hold After SDCLK
3
2.0 2.0 ns
t
SDTRSDK
Data Three-State After SDCLK
4
0.5t
CCLK
+ 2.0 0.5t
CCLK
+ 2.0 ns
t
SDENSDK
Data Enable After SDCLK
5
0.75t
CCLK
0.75t
CCLK
ns
t
SDCTR
Command Three-State After CLKIN 0.5t
CCLK
–1.5 0.5t
CCLK
+ 6.0 0.5t
CCLK
–1.5 0.5t
CCLK
+ 6.0 ns
t
SDCEN
Command Enable After CLKIN 2 5 2 5 ns
t
SDSDKTR
SDCLK Three-State After CLKIN 0 3 0 3 ns
t
SDSDKEN
SDCLK Enable After CLKIN 1 4 1 4 ns
t
SDATR
Address Three-State After CLKIN 0.25 t
CCLK
5 0.25t
CCLK
0.25 t
CCLK
5 0.25t
CCLK
ns
t
SDAEN
Address Enable After CLKIN 0.4 +7.2 0.4 +7.2 ns
1
For the second, third, and fourth rising edges of SDCLK delay from CLKIN, add appropriate number of SDCLK period to the t
DSDK1
and t
SSDKC1
values, depending upon the SDCKR
value and the core clock to CLKIN ratio.
2
Subtract t
CCLK
from result if value is greater than or equal to t
CCLK
.
3
Command = SDCKE, MSx, DQM, RAS, CAS, SDA10, and SDWE.
4
SDRAM Controller adds one SDRAM CLK three-stated cycle delay on a read, followed by a write.
5
Valid when DSP transitions to SDRAM master from SDRAM slave.
Table 27. SDRAM Interface — Bus Slave
Parameter Min Max Unit
Timing Requirements
t
SSDKC1
First SDCLK Rise after CLKOUT
1, 2, 3
SDCK  t
CCLK
0.5t
CCLK
 0.5 SDCKR  t
CCLK
0.25t
CCLK
+ 2.0 ns
t
SCSDK
Command Setup before SDCLK
4
2ns
t
HCSDK
Command Hold after SDCLK
4
1ns
1
For the second, third, and fourth rising edges of SDCLK delay from CLKOUT, add appropriate number of SDCLK period to the t
DSDK1
and t
SSDKC1
values, depending upon the
SDCKR value and the Core clock to CLKOUT ratio.
2
SDCKR = 1 for SDCLK equal to core clock frequency and SDCKR = 2 for SDCLK equal to half core clock frequency.
3
Subtract t
CCLK
from result if value is greater than or equal to t
CCLK
.
4
Command = SDCKE, RAS, CAS, and SDWE.