Datasheet

Rev. C | Page 4 of 60 | January 2013
ADSP-21161N
When using the DAGs to transfer data in SIMD mode, two data
values are transferred with each access of memory or the regis-
ter file.
SIMD is supported only for internal memory accesses and is not
supported for off-chip accesses.
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform single-cycle
instructions. The three units within each processing element are
arranged in parallel, maximizing computational throughput.
Single multifunction instructions execute parallel ALU and
multiplier operations. In SIMD mode, the parallel ALU and
multiplier operations occur in both processing elements. These
computation units support IEEE 32-bit single-precision float-
ing-point, 40-bit extended precision floating-point, and 32-bit
fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each pro-
cessing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the SHARC enhanced Harvard
architecture, allow unconstrained data flow between computa-
tion units and internal memory. The registers in PEX are
referred to as R0–R15 and in PEY as S0–S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21161N features an enhanced Harvard architecture
in which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 2). With the ADSP-21161N’s separate program and
data memory buses and on-chip instruction cache, the proces-
sor can simultaneously fetch four operands (two over each data
bus) and an instruction (from the cache), all in a single cycle.
Figure 2. System Diagram
DMA DEVICE
(OPTIONAL)
DATA
CLKOUT
DMAR2-1
DMAG2-1
ADDR
DATA
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
3
12
CLOCK
CLKIN
XTAL
IRQ2-0
2
CLK_CFG1-0
EBOOT
LBOOT
FLAG11-0
TIMEXP
CLKDBL
RESET JTAG
7
SBTS
ADSP-21161N
BMS
LINK
DEVICES
(2 MAX)
(OPTIONAL)
LXCLK
LXACK
LXDAT7-0
SCLK0
D0B
D0A
FS0
SERIAL
DEVICE
(OPTIONAL)
CS
BOOT
EPROM
(OPTIONAL)
ADDR
MEMORY
AND
PERIPHERALS
(OPTIONAL)
OE
DATA
CS
RD
RAS
ACK
BR6-1
RPBA
ID2-0
PA
HBG
HBR
SDWE
MS3-0
WR
DATA47-16
DATA
ADDR
CS
ACK
WE
ADDR23-0
D
A
T
A
C
O
N
T
R
O
L
A
D
D
R
E
S
S
BRST
SDRAM
(OPTIONAL)
SCLK1
D1B
D1A
FS1
SERIAL
DEVICE
(OPTIONAL)
SCLK2
D2B
D2A
FS2
SERIAL
DEVICE
(OPTIONAL)
SCLK3
D3B
D3A
FS3
SERIAL
DEVICE
(OPTIONAL)
SPICLK
MISO
MOSI
SPIDS
SPI
COMPATIBLE
DEVICE
(HOSTORSLAVE)
(OPTIONAL)
DATA
CAS
RAS
DQM
WE
ADDR
CS
A10
CKE
CLK
DQM
CAS
REDY
SDCKE
SDA10
SDCLK1-0
RSTOUT