Datasheet

Rev. C | Page 38 of 60 | January 2013
ADSP-21161N
Three-State Timing — Bus Master, Bus Slave
These specifications show how the memory interface is disabled
(stops driving) or enabled (resumes driving) relative to CLKIN
and the SBTS
pin. This timing is applicable to bus master transi-
tion cycles (BTC) and host transition cycles (HTC) as well as the
SBTS
pin.
During reset, the DSP will not respond to SBTS
, HBR, and MMS
accesses. Although the DSP will recognize HBR
asserted before
reset, a HBG
will not be returned by the DSP until after reset is
deasserted and the DSP completes bus synchronization.
Table 24. Three-State Timing — Bus Master, Bus Slave
Parameter Min Max Unit
Timing Requirements
t
STSCK
SBTS Setup Before CLKIN 6 ns
t
HTSCK
SBTS Hold After CLKIN 2 ns
Switching Characteristics
t
MIENA
Address/Select Enable After CLKIN High 1.5 9 ns
t
MIENS
Strobes Enable After CLKIN High
1
–1.5 +9 ns
t
MIENHG
HBG Enable After CLKIN 1.5 9 ns
t
MITRA
Address/Select Disable After CLKIN High 0.5t
CKOP
–20 0.5t
CKOP
–15 ns
t
MITRS
Strobes Disable After CLKIN High t
CKOP
–0.25t
CCLK
–17 t
CKOP
–0.25t
CCLK
–12.5 ns
t
MITRHG
HBG Disable After CLKIN
2
0.5t
CKOP
+Nt
CCLK
–20 0.5t
CKOP
+Nt
CCLK
–15 ns
t
DATEN
Data Enable After CLKIN
3
1.5 10 ns
t
DATTR
Data Disable After CLKIN
3
1.5 6 ns
t
ACKEN
ACK Enable After CLKIN High 1.5 9 ns
t
ACKTR
ACK Disable After CLKIN High 0.2 5 ns
t
CDCEN
CLKOUT Enable After CLKIN
2
0.5t
CKOP
+Nt
CCLK
0.5t
CKOP
+Nt
CCLK
+5 ns
t
CDCTR
CLKOUT Disable After CLKIN t
CKOP
–5 t
CKOP
ns
t
ATRHBG
Address/Select Disable Before HBG Low
4
1.5t
CKOP
–6 1.5t
CKOP
+2 ns
t
STRHBG
RD/WR/DMAGx Disable Before HBG Low
4
t
CKOP
+0.25t
CCLK
–4 t
CKOP
+0.25t
CCLK
+3 ns
t
BTRHBG
BMS Disable Before HBG Low
4
0.5t
CKOP
–4 0.5t
CKOP
+2 ns
t
MENHBG
Memory Interface Enable After HBG High
4
t
CKOP
–5 t
CKOP
+5 ns
1
Strobes = RD, WR, DMAGx.
2
Where N = 0.5, 1.0, 1.5 for 1:2, 1:3, and 1:4, respectively.
3
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
4
Memory Interface = Address, RD, WR, MSx, DMAGx, and BMS (in EPROM boot mode). BMS is only an output in EPROM boot mode.