Datasheet

Rev. C | Page 36 of 60 | January 2013
ADSP-21161N
Asynchronous Read/Write — Host to ADSP-21161N
Use these specifications for asynchronous host processor
accesses of an ADSP-21161N, after the host has asserted CS
and
HBR
(low). After HBG is returned by the ADSP-21161N, the
host can drive the RD
and WR pins to access the
ADSP-21161N’s IOP registers. HBR
and HBG are assumed low
for this timing. Although the DSP will recognize HBR
asserted
before reset, a HBG
will not be returned by the DSP until after
reset is deasserted and the DSP completes bus synchronization.
Note: Host internal memory access is not supported.
Table 22. Read Cycle
Parameter Min Max Unit
Timing Requirements
t
SADRDL
Address Setup and CS Low Before RD Low 0 ns
t
HADRDH
Address Hold and CS Hold Low After RD 2ns
t
WRWH
RD/WR High Width 3.5 ns
t
DRDHRDY
RD High Delay After REDY (O/D) Disable 0 ns
t
DRDHRDY
RD High Delay After REDY (A/D) Disable 0 ns
Switching Characteristics
t
SDATRDY
Data Valid Before REDY Disable from Low 2 ns
t
DRDYRDL
REDY (O/D) or (A/D) Low Delay After RD Low 10 ns
t
RDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read 1.5t
CCLK
ns
t
HDARWH
Data Disable After RD High 26ns
Table 23. Write Cycle
Parameter Min Max Unit
Timing Requirements
t
SCSWRL
CS Low Setup Before WR Low 0 ns
t
HCSWRH
CS Low Hold After WR High 0 ns
t
SADWRH
Address Setup Before WR High 6 ns
t
HADWRH
Address Hold After WR High 2 ns
t
WWRL
WR Low Width t
CCLK
 ns
t
WRWH
RD/WR High Width 3.5 ns
t
DWRHRDY
WR High Delay After REDY (O/D) or (A/D) Disable 0 ns
t
SDATWH
Data Setup Before WR High 5 ns
t
HDATWH
Data Hold After WR High 4 ns
Switching Characteristics
t
DRDYWRL
REDY (O/D) or (A/D) Low Delay After WR/CS Low
1
11 ns
t
RDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write
1
12 ns
1
Only when slave write FIFO is full.