Datasheet

ADSP-21161N
Rev. C | Page 31 of 60 | January 2013
Synchronous Read/Write — Bus Master
Use these specifications for interfacing to external memory sys-
tems that require CLKIN, relative to timing or for accessing a
slave ADSP-21161N (in multiprocessor memory space). When
accessing a slave ADSP-21161N, these switching characteristics
must meet the slave's timing requirements for synchronous
read/writes (see Synchronous Read/Write — Bus Slave on
Page 32). The slave ADSP-21161N must also meet these (bus
master) timing requirements for data and acknowledge setup
and hold times.
Table 18. Synchronous Read/Write — Bus Master
Parameter Min Max Unit
Timing Requirements
t
SSDATI
Data Setup Before CLKIN 5.5 ns
t
HSDATI
Data Hold After CLKIN 1 ns
t
SACKC
ACK Setup Before CLKIN 0.5t
CCLK
+3 ns
t
HACKC
ACK Hold After CLKIN 1 ns
Switching Characteristics
t
DADDO
Address, MSx, BMS, BRST, Delay After CLKIN 10 ns
t
HADDO
Address, MSx, BMS, BRST, Hold After CLKIN 1.5 ns
t
DRDO
RD High Delay After CLKIN 0.25t
CCLK
–1 0.25t
CCLK
+9 ns
t
DWRO
WR High Delay After CLKIN 0.25t
CCLK
–1 0.25t
CCLK
+9 ns
t
DRWL
RD/WR Low Delay After CLKIN 0.25t
CCLK
–1 0.25t
CCLK
+9 ns
t
DDATO
Data Delay After CLKIN 12.5 ns
t
HDATO
Data Hold After CLKIN 1.5 ns
Figure 19. Synchronous Read/Write — Bus Master
CLKIN
ACK
(IN)
DATA (OUT)
DATA
(IN)
WRITE CYCLE
READ CYCLE
t
HSDATI
t
SSDATI
t
DRDO
t
DWRO
t
HDATO
t
DDATO
t
SACKC
t
HACKC
t
HADDO
t
DADDO
ADDRESS
MSx, BRST
RD
WR
t
DRWL
t
DRWL