Datasheet

Rev. C | Page 24 of 60 | January 2013
ADSP-21161N
Clock Signals
The ADSP-21161N can use an external clock or a crystal. See
CLKIN pin description. The programmer can configure the
ADSP-21161N to use its internal clock generator by connecting
the necessary components to CLKIN and XTAL. Figure 12
shows the component connections used for a crystal operating
in fundamental mode.
Reset
Figure 12. 100 MHz Operation (Fundamental Mode Crystal)
Table 12. Reset
Parameter Min Max Unit
Timing Requirements
t
WRST
RESET Pulsewidth Low
1
1
Applies after the power-up sequence is complete.
4t
CK
ns
t
SRST
RESET Setup Before CLKIN High
2
2
Only required if multiple ADSP-21161Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple ADSP-21161Ns
communicating over the shared bus (through the external port), because the bus arbitration logic synchronizes itself automatically after reset.
8.5 ns
Figure 13. Reset
CLKIN XTAL
C2
27pF
C1
27pF
X1
SUGGESTED COMPONENTS FOR 100MHz OPERATION:
ECLIPTEK EC2SM-25.000M (SURFACE MOUNT PACKAGE)
ECLIPTEK EC-25.000M (THROUGH-HOLE PACKAGE)
C1 = 27pF
C2 = 27pF
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. THIS 25MHz
CRYSTAL GENERATES A 100MHz CCLK AND A 50MHz EP CLOCK
WITH CLKDBL ENABLED AND A 2:1 PLL MULTIPLY RATIO.
RESET
CLKIN
t
WRST
t
SRST