Datasheet

ADSP-21161N
Rev. C | Page 23 of 60 | January 2013
Clock Input
In systems that use multiprocessing or SBSRAM, CLKDBL can-
not be enabled nor can the systems use an external crystal as the
CLKIN source.
Do not use CLKOUT as the clock source for the SBSRAM
device. Using an external crystal in conjunction with CLKDBL
to generate a CLKOUT frequency is not supported. Negative
hold times can result from the potential skew between CLKIN
and CLKOUT.
Table 11. Clock Input
Parameter
100 MHz 110 MHz
Unit
Min Max Min Max
Timing Requirements
t
CK
CLKIN Period
1
20 238 18 238 ns
t
CKL
CLKIN Width Low
1
7.5 119 7 119 ns
t
CKH
CLKIN Width High
1
7.5 119 7 119 ns
t
CKRF
CLKIN Rise/Fall (0.4 V–2.0 V) 3 3 ns
t
CCLK
CCLK Period 10 30 9 30 ns
Switching Characteristics
t
DCKOO
CLKOUT Delay After CLKIN 0 2 0 2 ns
t
CKOP
CLKOUT Period t
CK
–1 t
CK
+1 t
CK
–1 t
CK
+1 ns
t
CKWH
CLKOUT Width High t
CKOP
/2–2 t
CKOP
/2+2 t
CKOP
/2–2 t
CKOP
/2+2 ns
t
CKWL
CLKOUT Width Low t
CKOP
/2–2 t
CKOP
/2+2 t
CKOP
/2–2 t
CKOP
/2+2 ns
1
CLKIN is dependent on the configuration of the CLKCFGx and CLKDBL pins to achieve desired t
CCLK
.
Figure 11. Clock Input
CLKIN
t
CKH
t
CK
t
CKL
CLKOUT
t
DCKOO
1
t
CKOP
1
t
CKWL
1
t
CKWH
1
CLKOUT
NOTES:
1. WHEN CLKDBL IS DIS ABLED, ANY SPECIFICATION TO CLKIN
APPLIES TO THE RISING EDGE, ONLY.
2. WHEN CLKDBL IS ENABLED, ANY SPECIFICATION TO CLKIN
APPLIES TO THE RISING OR FALLING EDGE.
t
DCKOO
2
t
CKOP
2
t
DCKOO
2
t
CKWH
2
t
CKWL
2