Datasheet

Rev. C | Page 22 of 60 | January 2013
ADSP-21161N
Power-Up Sequencing — Silicon Revision 1.2 and Greater
The timing requirements for DSP startup are given in Table 10.
During the power-up sequence of the DSP, differences in the
ramp-up rates and activation time between the two supplies can
cause current to flow in the I/O ESD protection circuitry. To
prevent damage to the ESD diode protection circuitry, Analog
Devices recommends including a bootstrap Schottky diode.
The bootstrap Schottky diode is connected between the 1.8 V
and 3.3 V power supplies as shown in Figure 9. It protects the
ADSP-21161N from partially powering the 3.3 V supply.
Including a Schottky diode will shorten the delay between
the supply ramps and thus prevent damage to the ESD diode
protection circuitry. With this technique, if the 1.8 V rail rises
ahead of the 3.3 V rail, the Schottky diode pulls the 3.3 V rail
along with the 1.8 V rail.
Figure 9. Dual Voltage Schottky Diode
3.3V I/O
VOLTAGE
REGULATOR
1.8VCORE
VOLTAGE
REGULATOR
V
DDEXT
V
DDINT
ADSP-21161N
DC INPUT
SOURCE
Table 10. Power-Up Sequencing Silicon Revision 1.2 and Greater (DSP Startup)
Parameter Min Max Unit
Timing Requirements
t
RSTVDD
RESET Low Before V
DDINT
/V
DDEXT
on 0 ns
t
IVDDEVDD
V
DDINT
on Before V
DDEXT
–50 +200 ms
t
CLKVDD
CLKIN Valid After V
DDINT
/V
DDEXT
Valid
1
0200ms
t
CLKRST
CLKIN Valid Before RESET Deasserted
2
10 μs
t
PLLRST
PLL Control Setup Before RESET Deasserted
3
20 μs
t
WRST
Subsequent RESET Low Pulsewidth
4
4t
CK
ns
Switching Requirements
t
CORERST
DSP core reset deasserted after RESET deasserted 4080t
CK
3, 5
1
Valid V
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.8 and 3.3 volt rails. Voltage ramp rates can vary from microseconds to hundreds of milliseconds
depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal, after meeting worst-case start-up timing of crystal oscillators. Refer to the crystal oscillator manufacturer's data sheet for start-up time.
Assume a 25 ms maximum oscillator start-up time if using the XTAL pin and internal oscillator circuit in conjunction with an external crystal.
3
Based on CLKIN cycles.
4
Applies after the power-up sequence is complete. Subsequent resets require a minimum of 4 CLKIN cycles for RESET to be held low in order to properly initialize and
propagate default states at all I/O pins.
5
The 4080 cycle count depends on t
SRST
specification in Table 12. If setup time is not met, one additional CLKIN cycle may be added to the core reset time, resulting in
4081 cycles maximum.
Figure 10. Power-Up Sequencing for Silicon Revision 1.2 and Greater (DSP Startup)
RESET
RSTOUT
CLKDBL
CLK_CFG1-0
CLKIN
t
RSTVDD
VDDEXT
VDDINT
t
PLLRST
t
CLKRST
t
CLKVDD
t
IVDDEVDD
t
CORERST