Datasheet

ADSP-21161N
Rev. C | Page 21 of 60 | January 2013
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• The number of output pins that switch during each cycle
(O)
• The maximum frequency at which they can switch (f)
• Their load capacitance (C)
• Their voltage swing (V
DD
)
and is calculated by:
The load capacitance should include the processor package
capacitance (C
IN
). The switching frequency includes driving the
load high and then back low. At a maximum rate of 1/t
CK
,
address and data pins can drive high and low, while writing to a
SDRAM memory.
Example: Estimate P
EXT
with the following assumptions:
• A system with one bank of external memory (32 bit)
•Two 1M ⴛ 16 SDRAM chips are used, each with a load of
10 pF (ignoring trace capacitance)
• External Data Memory writes can occur every cycle at a
rate of 1/t
CK
with 50% of the pins switching
• The bus cycle time is 55 MHz
• The external SDRAM clock rate is 110 MHz
• Ignoring SDRAM refresh cycles
• Addresses are incremental and on the same page
The P
EXT
equation is calculated for each class of pins that can
drive, as shown in Table 9.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
Where:
P
EXT
is from Table 9.
P
INT
is I
DDINT
× 1.8 V, using the calculation I
DDINT
listed in Power
Dissipation on Page 20.
P
PLL
is AI
DD
× 1.8 V, using the value for AI
DD
listed in the Electri-
cal Characteristics on Page 18.
Note that the conditions causing a worst-case P
EXT
are different
from those causing a worst-case P
INT
. Maximum P
INT
cannot
occur while 100% of the output pins are switching from all ones
to all zeros. Note also that it is not common for an application to
have 100% or even 50% of the outputs switching
simultaneously.
Table 8. Operation Types Versus Input Current
Operation Peak Activity
1
(I
DDINPEAK
)High Activity
1
(I
DDINHIGH
)Low Activity
1
(I
DDINLOW
)
Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core Memory Access
2
2 per t
CK
cycle (DM64 and PM64) 1 per t
CK
cycle (DM64) None
Internal Memory DMA 1 per 2 t
CCLK
cycles 1 per 2 t
CCLK
cycles N/A
External Memory DMA 1 per external port cycle (32) 1 per external port cycle (32) N/A
Data bit pattern for core
memory access and DMA
Worst case Random N/A
1
The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.
2
These assume a 2:1 core clock ratio. For more information on ratios and clocks (t
CK
and t
CCLK
), see the timing ratio definitions on Page 19.
P
EXT
OC V
DD
2
 f=
P
TOTAL
P
EXT
P
INT
P
PLL
++=
Table 9. External Power Calculations—110 MHz Instruction Rate
Pin Type Number of Pins % Switching ⴛ C ⴛ f ⴛ V
DD
2
= P
EXT
Address 11 20 24.7 pF 55 MHz 10.9 V = 0.033 W
MSx
4 0 24.7 pF N/A 10.9 V = 0.000 W
SDWE
1 0 24.7 pF N/A 10.9 V = 0.000 W
Data 32 50 14.7 pF 55 MHz 10.9 V = 0.141 W
SDCLK0 1 100 24.7 pF 110 MHz 10.9 V = 0.030 W
P
EXT
= 0.204 W