Datasheet

Rev. C | Page 20 of 60 | January 2013
ADSP-21161N
POWER DISSIPATION
Total power dissipation has two components: one due to inter-
nal circuitry and one due to the switching of external output
drivers.
Internal power dissipation depends on the instruction execution
sequence and the data operands involved. Using the current
specifications (I
DDINPEAK
, I
DDINHIGH
, I
DDINLOW
, I
DDIDLE
) from the
Electrical Characteristics on Page 18 and the current-versus-
operation information in Table 8, the programmer can estimate
the ADSP-21161N’s internal power supply (V
DDINT
) input cur-
rent for a specific application, according to the following
formula:
% Peak  I
DD - INPEAK
% High  I
DD - INHIGH
% Low  I
DD - INLOW
+ % Peak  I
DD - IDLE
= I
DDINT
Figure 8. Core Clock and System Clock Relationship to CLKIN
Table 7. CLKOUT and CCLK Clock Generation Operation
Timing Requirements Description
1
Calculation
CLKIN Input Clock 1/t
CK
CLKOUT External Port System Clock 1/t
CKOP
PLLICLK PLL Input Clock 1/t
PLLIN
CCLK Core Clock 1/t
CCLK
t
CK
CLKIN Clock Period 1/CLKIN
t
CCLK
(Processor) Core Clock Period 1/CCLK
t
LCLK
Link Port Clock Period (t
CCLK
) LR
t
SCLK
Serial Port Clock Period (t
CCLK
)  SR
t
SDK
SDRAM Clock Period (t
CCLK
)  SDCKR
t
SPICLK
SPI Clock Period (t
CCLK
)  SPIR
1
where:
LR = link port-to-core clock ratio (1, 2, 3, or 1:4, determined by LxCLKD)
SR = serial port-to-core clock ratio (wide range, determined by CLKDIV)
SDCKR = SDRAM-to-Core Clock Ratio (1:1 or 1:2, determined by SDCTL register)
SPIR = SPI-to-Core Clock Ratio (wide range, determined by SPICTL register)
LCLK = Link Port Clock
SCLK = Serial Port Clock
SDK = SDRAM Clock
SPICLK = SPI Clock
CLOCK DOUBLER
x1, x2
RATIOS
x2, x3, x4
PLL
ASYNCHRONOUS EP
HOST
SRAM
SYNCHRONOUS EP
MULTIPROCESSING
SBSRAM
HARDWARE
INTERRUPT
I/O FLAG
TIMER
P
L
L
I
C
L
K
(
4
.
2
–
5
0
M
H
z
)
CLKDBL
CLKOUT CLK_CFG1–0
CLKIN
(CRYSTAL OSCILLATOR
4.2–55 MHz)
XTAL
(QUARTZ CRYSTAL
27.5 MHz MAX)
CORE
I/O PROCESSOR
SPI
x1/8 MAX
SERIAL PORTS
x1/2 MAX
SDRAM
x1, x1/2
LINK PORTS
x1, x1/2, x1/3, x1/4
C
C
L
K
(
3
3
.
3
–
1
1
0
M
H
z
)