Datasheet

Rev. C | Page 18 of 60 | January 2013
ADSP-21161N
ELECTRICAL CHARACTERISTICS
Parameter Description Test Conditions Min Max Unit
V
OH
High Level Output Voltage
1
@ V
DDEXT
= Min, I
OH
= –2.0 mA
2
2.4 V
V
OL
Low Level Output Voltage
1
@ V
DDEXT
= Min, I
OL
= 4.0 mA
2
0.4 V
I
IH
High Level Input Current
3, 4
@ V
DDEXT
= Max, V
IN
= V
DDEXT
Max 10 μA
I
IL
Low Level Input Current
3
@ V
DDEXT
= Max, V
IN
= 0 V 10 μA
I
IHC
CLKIN High Level Input Current
5
@ V
DDEXT
= Max, V
IN
= V
DDEXT
Max 35 μA
I
ILC
CLKIN Low Level Input Current
5
@ V
DDEXT
= Max, V
IN
= 0 V 35 μA
I
IKH
Keeper High Load Current
6
@ V
DDEXT
= Max, V
IN
= 2.0 V –250 –100 μA
I
IKL
Keeper Low Load Current
6
@ V
DDEXT
= Max, V
IN
= 0.8 V 50 200 μA
I
IKH-OD
Keeper High Overdrive Current
6, 7, 8
@ V
DDEXT
= Max –300 μA
I
IKL-OD
Keeper Low Overdrive Current
6, 7, 8
@ V
DDEXT
= Max 300 μA
I
ILPU
Low Level Input Current Pull-Up
4
@ V
DDEXT
= Max, V
IN
= 0 V 350 μA
I
OZH
Three-State Leakage Current
9, 10, 11
@ V
DDEXT
= Max, V
IN
= V
DDEXT
Max 10 μA
I
OZL
Three-State Leakage Current
9, 12, 13
@ V
DDEXT
= Max, V
IN
= 0 V 10 μA
I
OZLPU1
Three-State Leakage Current Pull-Up1
10
@ V
DDEXT
= Max, V
IN
= 0 V 500 μA
I
OZLPU2
Three-State Leakage Current Pull-Up2
11
@ V
DDEXT
= Max, V
IN
= 0 V 350 μA
I
OZHPD1
Three-State Leakage Current Pull-Down1
12
@ V
DDEXT
= Max, V
IN
= V
DDEXT
Max 350 μA
I
OZHPD2
Three-State Leakage Current Pull-Down2
13
@ V
DDEXT
= Max, V
IN
= V
DDEXT
Max 500 μA
I
DD-INPEAK
Supply Current (Internal)
14, 15
t
CCLK
= 9.0 ns, V
DDINT
= Max
t
CCLK
= 10.0 ns, V
DDINT
= Max
965
900
mA
I
DD-INHIGH
Supply Current (Internal)
15, 16
t
CCLK
= 9.0 ns, V
DDINT
= Max
t
CCLK
= 10.0 ns, V
DDINT
= Max
700
650
mA
I
DD-INLOW
Supply Current (Internal)
15, 17
t
CCLK
= 9.0 ns, V
DDINT
= Max
t
CCLK
= 10.0 ns, V
DDINT
= Max
535
500
mA
I
DD-IDLE
Supply Current (Idle)
15, 18
t
CCLK
= 9.0 ns, V
DDINT
= Max
t
CCLK
= 10.0 ns, V
DDINT
= Max
425
400
mA
AI
DD
Supply Current (Analog)
19
@ AV
DD
= Max 10 mA
C
IN
Input Capacitance
20, 21
f
IN
= 1 MHz, T
CASE
= 25°C, V
IN
= 1.8 V 4.7 pF
1
Applies to output and bidirectional pins: DATA47–16, ADDR23–0, MS3–0, RD, WR, ACK, DQM, FLAG11–0, HBG, REDY, DMAG1, DMAG2,
BR6–1, BMSTR, PA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE, SDA10, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, BMS, SDCLKx, SDCKE, EMU, XTAL,
TDO, CLKOUT, TIMEXP, RSTOUT.
2
See Output Drive Currents on Page 54 for typical drive current capabilities.
3
Applies to input pins: DATA47–16, ADDR23–0, MS3–0, SBTS, IRQ2–0, FLAG11–0, HBG, HBR, CS, BR6–1, ID2–0, RPBA, BRST, FSx, DxA, DxB, SCLKx, RAS, CAS, SDWE,
SDCLK0, LxDAT7–0, LxCLK, LxACK, SPICLK, MOSI, MISO, SPIDS
, EBOOT, LBOOT, BMS, SDCKE, CLK_CFGx, CLKDBL, TCK, RESET, CLKIN.
4
Applies to input pins with 20 k internal pull-ups: RD, WR, ACK, DMAR1, DMAR2, PA, TRST, TMS, TDI.
5
Applies to CLKIN only.
6
Applies to all pins with keeper latches: ADDR23–0, DATA47–0, MS3–0, BRST, CLKOUT.
7
Current required to switch from kept high to low or from kept low to high.
8
Characterized, but not tested.
9
Applies to three-statable pins: DATA47–16, ADDR23–0, MS3–0, CLKOUT, FLAG11–0, REDY, HBG, BMS, BR6–1, RAS, CAS, SDWE, DQM, SDCLKx, SDCKE, SDA10,
BRST.
10
Applies to three-statable pins with 20 kpull-ups: RD, WR, DMAG1, DMAG2, PA.
11
Applies to three-statable pins with 50 k internal pull-ups: DxA, DxB, SCLKx, SPICLK., EMU, MISO, MOSI.
12
Applies to three-statable pins with 50 k internal pull-downs: LxDAT7–0 (below Revision1.2), LxCLK, LxACK. Use I
OZHPD2
for Rev. 1.2 and higher.
13
Applies to three-statable pins with 20 k internal pull-downs: LxDAT7-0 (Revision 1.2 and higher).
14
The test program used to measure I
DDINPEAK
represents worst-case processor operation and is not sustainable under normal application conditions. Actual internal power
measurements made using typical applications are less than specified. For more information, see Power Dissipation on Page 20.
15
Current numbers are for V
DDINT
and AVDD supplies combined.
16
I
DDINHIGH
is a composite average based on a range of high activity code. For more information, see Power Dissipation on Page 20.
17
I
DDINLOW
is a composite average based on a range of low activity code. For more information, see Power Dissipation on Page 20.
18
Idle denotes ADSP-21161N state during execution of IDLE instruction. For more information, see Power Dissipation on Page 20.
19
Characterized, but not tested.
20
Applies to all signal pins.
21
Guaranteed, but not tested.