Datasheet

ADSP-21160N
–40– REV. 0
Output Drive Currents
Figure 27 shows typical I–V characteristics for the output drivers
of the ADSP-21160N. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Power Dissipation
Total power dissipation has two components, one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation is dependent on the instruction
execution sequence and the data operands involved. Using the
current specifications (I
DD-INPEAK
, I
DD-INHIGH
, I
DD-INLOW
, I
DD-IDLE
)
from Electrical Characteristics on Page 14 and the current-
versus-operation information in Table 29, engineers can
estimate the ADSP-21160N’s internal power supply (V
DDINT
)
input current for a specific application, according to the formula.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
• the number of output pins that switch during each
cycle (O)
• the maximum frequency at which they can switch (f)
• their load capacitance (C)
• their voltage swing (V
DD
)
and is calculated by:
P
EXT
= O × C × V
DD
2
× f
The load capacitance should include the processor’s package
capacitance (C
IN
). The switching frequency includes driving the
load h igh and the n b ack low. Address and data pins can drive high
and low at a maximum rate of 1/(2t
CK
). The write strobe can
switch every cycle at a frequency of 1/t
CK
. Select pins switch at
1/(2t
CK
), but selects can switch on each cycle.
Example: Estimate P
EXT
with the following assumptions:
• A system with one bank of external data memory—asyn-
chronous RAM (64-bit)
• Four 64K × 16 RAM chips are used, each with a load
of 10 pF
• External data memory writes occur every other cycle, a
rate of 1/(2 t
CK
), with 50% of the pins switching
• The bus cycle time is 50 MHz (t
CK
= 20 ns).
The P
EXT
equation is calculated for each class of pins that
can drive, as shown in Table 30.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
P
TOTAL
= P
EXT
+ P
INT
+ P
PLL
Figure 27. Typical Drive Currents
SWEEP (V
DDEXT
)VOLTAGE–V
03.50.5 1 1.5 2 2.5 3
S
O
U
R
C
E
(
V
D
D
E
X
T
)
C
U
R
R
E
N
T
–
m
A
–80
–60
–40
–20
0
20
40
60
80
V
DDEXT
= 3.47V, –45°C
V
DDEXT
=3.47V,–45°C
V
DDEXT
=3.3V,25°C
V
DDEXT
= 3.11V, 115°C
V
OH
V
DDEXT
= 3.11V, 115°C
V
DDEXT
= 3.3V, 25°C
V
OL
% Peak I
DD-INPEAK
×
% High I
DD-INHIGH
×
% Low I
DD-INLOW
×
+ % Idle I
DD-IDLE
×
I
DDINT
---------------------------------------------------- -
Table 29. ADSP-21160N Operation Types vs. Input Current
Operation Peak Activity
1
High Activity
1
Low Activity
1
Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core Memory Access
2
2 per t
CK
Cycle
(DM  64 and PM  64)
1 per t
CK
Cycle
(DM  64)
None
Internal Memory DMA 1 per 2 t
CCLK
Cycles 1 per 2 t
CCLK
Cycles None
External Memory DMA 1 per External Port Cycle (64) 1 per External Port Cycle ( 64) None
Data Bit Pattern for Core
Memory Access and DMA
Worst Case Random N/A
1
Peak Activity=I
DD-INPEAK
, High Activity=I
DD-INHIGH
, and Low Activity=I
DD-INLOW
. The state of the PEYEN bit (SIMD versus SISD mode) does not
influence these calculations.
2
These assume a 2:1 core clock ratio. For more information on ratios and clocks (t
CK
and t
CCLK
), see the timing ratio definitions on Page 16.