Datasheet

ADSP-21160N
–34– REV. 0
Link Ports —Receive, Transmit
For Link Ports, see Table 19, Table 20, Figure 22, and
Figure 23. Calculation of link receiver data setup and hold,
relative to link clock, is required to determine the maximum
allowable skew that can be introduced in the transmission path,
between LDATA and LCLK. Setup skew is the maximum delay
that can be introduced in LDATA, relative to LCLK (setup
skew = t
LCLKTWH
minimum – t
DLDCH
–t
SLDCL
). Hold skew is the
maximum delay that can be introduced in LCLK, relative to
LDATA (hold skew = t
LCLKTWL
minimum + t
HLDCH
–t
HLDCL
). Cal-
culations made directly from speed specifications result in
unrealistically small skew times, because they include multiple
tester guardbands.
Note that there is a two-cycle effect latency between the link port
enable instruction and the DSP enabling the link port.
Table 19. Link Ports—Receive
Parameter Min Max Unit
Timing Requirements
t
SLDCL
Data Setup Before LCLK Low 2.5 ns
t
HLDCL
Data Hold After LCLK Low 3 ns
t
LCLKIW
LCLK Period t
LCLK
ns
t
LCLKRWL
LCLK Width Low 4 ns
t
LCLKRWH
LCLK Width High 4 ns
Switching Characteristics
t
DLALC
LACK Low Delay After LCLK High
1
917ns
1
LACK goes low with t
DLALC
relative to rise of LCLK after first nibble, but does not go low if the receiver’s link buffer is not about to fill.
Table 20. Link Ports—Transmit
Parameter Min Max Unit
Timing Requirements
t
SLACH
LACK Setup Before LCLK High 14 ns
t
HLACH
LACK Hold After LCLK High –2 ns
Switching Characteristics
t
DLDCH
Data Delay After LCLK High 4 ns
t
HLDCH
Data Hold After LCLK High –2 ns
t
LCLKTWL
LCLK Width Low 0.5t
LCLK
–.5 0.5t
LCLK
+.5 ns
t
LCLKTWH
LCLK Width High 0.5t
LCLK
–.5 0.5t
LCLK
+.5 ns
t
DLACLK
LCLK Low Delay After LACK High 0.5t
LCLK
+4 3/2t
LCLK
+11 ns
Figure 22. Link Ports—Receive
LCLK
LDAT(7:0)
LACK (OUT)
RECEIVE
IN
t
SLDCL
t
HLDCL
t
LCLKRWH
t
DLALC
t
LCLKRWL
t
LCLKIW