Datasheet

ADSP-21160N
–22– REV. 0
Memory Write—Bus Master
See Table 11 and Figure 14. Use these specifications for asyn-
chronous interfacing to memories (and memory-mapped
peripherals) without reference to CLKIN. These specifications
apply when the ADSP-21160N is the bus master accessing
external memory space in asynchronous access mode. Note that
timing for ACK, DATA,
RDx , WRx , and DMAGx strobe timing
parameters only applies to asynchronous access mode.
Table 11. Memory Write—Bus Master
Parameter Min Max Unit
Timing Requirements
t
DAAK
ACK Delay from Address, Selects
1, 2
t
CK
–0.5t
CCLK
–12+W ns
t
DSAK
ACK Delay from WRx Low
1
t
CK
– 0.75t
CCLK
–11+W ns
t
SAKC
ACK Setup to CLKIN
1
0.5t
CCLK
+3 ns
t
HAKC
ACK Hold After CLKIN
1
1ns
Switching Characteristics
t
DAWH
Address, CIF, Selects to WRx
Deasserted
2
t
CK
– 0.25t
CCLK
–3+W ns
t
DAWL
Address, CIF, Selects to WRx Low
2
0.25t
CCLK
–3 ns
t
WW
WRx Pulsewidth t
CK
–0.5t
CCLK
–1+W ns
t
DDWH
Data Setup before WRx High t
CK
–0.5t
CCLK
–1+W ns
t
DWHA
Address Hold after WRx Deasserted 0.25t
CCLK
–1+H ns
t
DWHD
Data Hold after WRx Deasserted 0.25t
CCLK
–1+H ns
t
DATRWH
Data Disable after WRx Deasserted
3
0.25t
CCLK
– 2+H 0.25t
CCLK
+2+H ns
t
WWR
WRx High to WRx, RDx, DMAGx Low 0.5t
CCLK
–1+HI ns
t
DDWR
Data Disable before WRx or RDx Low 0.25t
CCLK
–1+I ns
t
WDE
WRx Low to Data Enabled –0.25t
CCLK
–1 ns
W = (number of wait states specified in WAIT register) × t
CK
.
H = t
CK
(if an address hold cycle occurs, as specified in WAIT register; otherwise H = 0).
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
I = t
CK
(if a bus idle cycle occurs, as specified in WAIT register; otherwise I = 0).
1
ACK Delay/Setup: User must meet t
DAAK
or t
DSAK
or t
SAKC
for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
2
The falling edge of MSx, BMS is referenced.
3
See Example System Hold Time Calculation on Page 41 for calculation of hold times given capacitive and dc loads.
Figure 14. Memory Write—Bus Master
t
DATRWH
RDx
ACK
DATA
WRx
ADDRESS
MSx, BMS,
CIF
t
DAWL
t
WW
t
DAAK
t
WDE
t
DDWR
t
DWHA
t
DAWH
t
DSAK
t
DDWH
t
DWHD
t
SAKC
CLKIN
DMAGx
t
HAKC
t
WWR