Datasheet
ADSP-21160N
–2– REV. 0
KEY FEATURES (continued)
IEEE 1149.1 JTAG Standard Test Access Port and On-Chip
Emulation
400-Ball 27 mm 27 mm Metric PBGA Package
200 Million Fixed-Point MACs Sustained Performance
Single Instruction Multiple Data (SIMD)
Architecture Provides:
Two Computational Processing Elements
Concurrent Execution—Each Processing Element
Executes the Same Instruction, but Operates on
Different Data
Code Compatibility—at Assembly Level, Uses the
Same Instruction Set as the ADSP-2106x
SHARC DSPs
Parallelism in Buses and Computational Units Allows:
Single-Cycle Execution (with or without SIMD) of: A
Multiply Operation, An ALU Operation, A Dual
Memory Read or Write, and An Instruction Fetch
Transfers Between Memory and Core at up to Four
32-Bit Floating- or Fixed-Point Words per Cycle
Accelerated FFT Butterfly Computation Through a
Multiply with Add and Subtract
4M Bits On-Chip Dual-Ported SRAM for Independent
Access by Core Processor, Host, and DMA
DMA Controller Supports:
14 Zero-Overhead DMA Channels for Transfers Between
ADSP-21160N Internal Memory and External Memory,
External Peripherals, Host Processor, Serial Ports, or
Link Ports
64-Bit Background DMA Transfers at Core Clock Speed,
in Parallel with Full-Speed Processor Execution
Host Processor Interface to 16- and 32-Bit
Microprocessors
4G Word Address Range for Off-Chip Memory
Memory Interface Supports Programmable Wait State
Generation and Page-Mode for Off-Chip Memory
Multiprocessing Support Provides:
Glueless Connection for Scalable DSP Multiprocessing
Architecture
Distributed On-Chip Bus Arbitration for Parallel Bus
Connect of up to Six ADSP-21160Ns Plus Host
Six Link Ports for Point-to-Point Connectivity and Array
Multiprocessing
Serial Ports Provide:
Two 50M Bits/s Synchronous Serial Ports with
Companding Hardware
Independent Transmit and Receive Functions
TDM Support for T1 and E1 Interfaces
64-Bit Wide Synchronous External Port Provides:
Glueless Connection to Asynchronous and SBSRAM
External Memories
Up to 50 MHz Operation