Datasheet

ADSP-21160N
–18– REV. 0
Clock Input
For Clock Input, see Table 5 and Figure 8.
Reset
For Reset, see Table 6 and Figure 9.
Table 5. Clock Input
Parameter
100 MHz
UnitMin Max
Timing Requirements
t
CK
CLKIN Period 20 80 ns
t
CKL
CLKIN Width Low 7.5 40 ns
t
CKH
CLKIN Width High 7.5 40 ns
t
CKRF
CLKIN Rise/Fall (0.4 V–2.0 V) 3 ns
t
CCLK
Core Clock Period 10 30 ns
Figure 8. Clock Input
CLKIN
t
CKH
t
CKL
t
CK
Table 6. Reset
Parameter Min Max Unit
Timing Requirements
t
WRST
RESET Pulsewidth Low
1
4t
CK
ns
t
SRST
RESET Setup Before CLKIN High
2
8ns
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 µs while RESET is
low, assuming stable V
DD
and CLKIN (not including start-up time of external clock oscillator).
2
Only required if multiple ADSP-21160Ns must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple
ADSP-21160Ns communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself
after reset.
Figure 9. Reset
CLKIN
RESET
t
WRST
t
SRST