Datasheet

–17–REV. 0
ADSP-21160N
Table 4. Power-up Sequencing
Parameter Min Max Unit
Timing Requirements
t
RSTVDD
RESET Low Before V
DDINT
/V
DDEXT
on 0 ns
t
IVDDEVDD
V
DDINT
on Before V
DDEXT
– 50 +200 ms
t
CLKVDD
CLKIN Running After valid V
DDINT
/V
DDEXT
1
0 200 ms
t
CLKRST
CLKIN Valid Before RESET Deasserted 10
2
µs
t
PLLRST
PLL Control Setup Before RESET Deasserted 20
3
µs
Switching Characteristics
t
CORERST
DSP Core Reset Deasserted After RESET Deasserted 4096t
CK
3, 4
ms
1
Valid V
DDINT
/V
DDEXT
assumes that the supplies are fully ramped to their 1.9 V and 3.3 V rails. Voltage ramp rates can vary from microseconds to hundreds
of milliseconds, depending on the design of the power supply subsystem.
2
Assumes a stable CLKIN signal after meeting worst-case start-up timing of oscillators. Refer to your oscillator manufacturer’s data sheet for start-up time.
3
Based on CLKIN cycles.
4
CORERST is an internal signal only. The 4096 cycle count is dependent on t
SRST
specification. If setup time is not met, one additional CLKIN cycle may
be added to the core reset time, resulting in 4097 cycles maximum.
Figure 6. Power-up Sequencing
Figure 7. Dual Voltage Schottky Diode
CLKIN
RESET
t
RSTVDD
V
DDEXT
V
DDINT
t
IVDDEVDD
t
CLKVDD
t
CLKRST
t
PLLRST
t
CORERST
CLK_CFG3-0
CORERST
3.3V I/O
VOLTAGE REGULATOR
1.9V CORE
VOLTAGE REGULATOR
ADSP-21160
V
DDEXT
V
DDINT