Datasheet

–37–REV. 0
ADSP-21160N
Table 26. Serial Ports—Internal Clock
Parameter Min Max Unit
Switching Characteristics
t
DFSI
TFS Delay After TCLK (Internally Generated TFS)
1
4.5 ns
t
HOFSI
TFS Hold After TCLK (Internally Generated TFS)
1
–1.5 ns
t
DDTI
Transmit Data Delay After TCLK
1
7.5 ns
t
HDTI
Transmit Data Hold After TCLK
1
0ns
t
SCLKIW
TCLK/RCLK Width 0.5t
SCLK
–1.5 0.5t
SCLK
+1.5 ns
1
Referenced to drive edge.
Table 27. Serial Ports—External Late Frame Sync
Parameter Min Max Unit
Switching Characteristics
t
DDTLFSE
Data Delay from Late External TFS or External RFS with
MCE = 1, MFD = 0
1
13 ns
t
DDTENFS
Data Enable from Late FS or MCE = 1, MFD = 0
1
1.0 ns
1
MCE = 1, TFS enable and TFS valid follow t
DDTLFSE
and t
DDTENFS
.
Figure 24. Serial Ports—External Late Frame Sync
DRIVE SAMPLE DRIVE
TCLK
TFS
DT
DRIVE SAMPLE DRIVE
LATE EXTERNAL TFS
EXTERNAL RFS WITH MCE = 1, MFD = 0
1ST BIT 2ND BITDT
RCLK
RFS
1ST BIT 2ND BIT
t
HOFSE/I
t
SFSE/I
t
DDTE/I
t
DDTENFS
t
DDTLFSE
t
HDTE/I
t
HOFSE/I
t
SFSE/I
t
DDTE/I
TDDTENFS
t
DDTLFSE
t
HDTE/I