Datasheet

ADSP-21160N
–32– REV. 0
DMA Handshake
See Table 18 and Figure 21. These specifications describe the
three DMA handshake modes. In all three modes,
DMARx is
used to initiate transfers. For handshake mode,
DMAGx controls
the latching or enabling of data externally. For external hand-
shake mode, the data transfer is controlled by the ADDR31–0,
RDx , WRx , PAGE, MS3–0 , ACK, and DMAG x signals. For
Paced Master mode, the data transfer is controlled by
ADDR31–0,
RDx , WRx , MS3–0 , and ACK (not DMAG ). For
Paced Master mode, the Memory Read-Bus Master, Memory
Write-Bus Master, and Synchronous Read/Write-Bus Master
timing specifications for ADDR31–0,
RDx , WRx , MS3–0 ,
PAGE, DATA63–0, and ACK also apply.
Table 18. DMA Handshake
Parameter Min Max Unit
Timing Requirements
t
SDRC
DMARx Setup Before CLKIN
1
3ns
t
WDR
DMARx Width Low (Nonsynchronous)
2
0.5t
CCLK
+2.5 ns
t
SDATDGL
Data Setup After DMAGx Low
3
t
CK
–0.5t
CCLK
–7 ns
t
HDATIDG
Data Hold After DMAGx High 2 ns
t
DATDRH
Data Valid After DMARx High
3
t
CK
+3 ns
t
DMARLL
DMARx Low Edge to Low Edge
4
t
CK
ns
t
DMARH
DMARx Width High
2
0.5t
CCLK
+1 ns
Switching Characteristics
t
DDGL
DMAGx Low Delay After CLKIN 0.25t
CCLK
+1 0.25t
CCLK
+9 ns
t
WDGH
DMAGx High Width 0.5t
CCLK
–1+HI ns
t
WDGL
DMAGx Low Width t
CK
–0.5t
CCLK
–1 ns
t
HDGC
DMAGx High Delay After CLKIN t
CK
– 0.25t
CCLK
+1.5 t
CK
– 0.25t
CCLK
+9 ns
t
VDATDGH
Data Valid Before DMAGx High
5
t
CK
– 0.25t
CCLK
–8 t
CK
– 0.25t
CCLK
+5 ns
t
DATRDGH
Data Disable After DMAGx High
6
0.25t
CCLK
– 3 0.25t
CCLK
+1.5 ns
t
DGWRL
WRx Low Before DMAGx Low –1.5 2 ns
t
DGWRH
DMAGx Low Before WRx High t
CK
–0.5t
CCLK
–2+W ns
t
DGWRR
WRx High Before DMAGx High
7
–1.5 2 ns
t
DGRDL
RDx Low Before DMAGx Low –1.5 2 ns
t
DRDGH
RDx Low Before DMAGx High t
CK
–0.5t
CCLK
–2+W ns
t
DGRDR
RDx High Before DMAGx High
7
–1.5 2 ns
t
DGWR
DMAGx High to WRx, RDx, DMAGx
Low
0.5t
CCLK
–2+HI ns
t
DADGH
Address/Select Valid to DMAGx High 15.5 ns
t
DDGHA
Address/Select Hold after DMAGx High 1 ns
W = (number of wait states specified in WAIT register)  t
CK
.
HI = t
CK
(if data bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
1
Only required for recognition in the current cycle.
2
Maximum throughput using DMARx/DMAGx handshaking equals t
WDR
+ t
DMARH
= (0.5t
CCLK
+1) + (0.5t
CCLK
+1)=10.0 ns (100 MHz). This throughput
limit applies to non-synchronous access mode only.
3
t
SDATDGL
is the data setup requirement if DMARx is not being used to hold off completion of a write. Otherwise, if DMARx low holds off completion of
the write, the data can be driven t
DATDRH
after DMARx is brought high.
4
Use t
DMARLL
if DMARx transitions synchronous with CLKIN. Otherwise, use t
WDR
and t
DMARH
.
5
t
VDATDGH
is valid if DMARx is not being used to hold off completion of a read. If DMARx is used to prolong the read, then
t
VDATDGH
=t
CK
–.25t
CCLK
–8+(n×t
CK
) where n equals the number of extra cycles that the access is prolonged.
6
See Example System Hold Time Calculation on Page 41 for calculation of hold times given capacitive and dc loads.
7
This parameter applies for synchronous access mode only.