Datasheet

ADSP-21160N
–28– REV. 0
Asynchronous Read/Write—Host to ADSP-21160N
Use these specifications (Table 15, Table 16, Figure 18, and
Figure 19) for asynchronous host processor accesses of an
ADSP-21160N, after the host has asserted
CS and HBR (low).
After
HBG is returned by the ADSP-21160N, the host can drive
the
RDx and WRx pins to access the ADSP-21160N’s internal
memory or IOP registers.
HBR and HBG are assumed low for
this timing.
Table 15. Read Cycle
Parameter Min Max Unit
Timing Requirements
t
SADRDL
Address Setup/CS Low Before RDx Low 0 ns
t
HADRDH
Address Hold/CS Hold Low After RDx 2ns
t
WRWH
RDx/WRx High Width 5ns
t
DRDHRDY
RDx High Delay After REDY (O/D) Disable 0 ns
t
DRDHRDY
RDx High Delay After REDY (A/D) Disable 0 ns
Switching Characteristics
t
SDATRDY
Data Valid Before REDY Disable from Low 2 ns
t
DRDYRDL
REDY (O/D) or (A/D) Low Delay After RDx Low 11 ns
t
RDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read t
CK
– 4 ns
t
HDARWH
Data Disable After RDx High 1.5 6 ns
Table 16. Write Cycle
Parameter Min Max Unit
Timing Requirements
t
SCSWRL
CS Low Setup Before WRx Low 0 ns
t
HCSWRH
CS Low Hold After WRx High 0 ns
t
SADWRH
Address Setup Before WRx High 6 ns
t
HADWRH
Address Hold After WRx High 2 ns
t
WWRL
WRx Low Width t
CCLK
+1 ns
t
WRWH
RDx/WRx High Width 5 ns
t
DWRHRDY
WRx High Delay After REDY (O/D) or (A/D) Disable 0 ns
t
SDATWH
Data Setup Before WRx High 5 ns
t
HDATWH
Data Hold After WRx High 4 ns
Switching Characteristics
t
DRDYWRL
REDY (O/D) or (A/D) Low Delay After WRx/CS Low 11 ns
t
RDYPWR
REDY (O/D) or (A/D) Low Pulsewidth for Write 5.75 + 0.5t
CCLK
ns