Datasheet

–25–REV. 0
ADSP-21160N
Synchronous Read/Write—Bus Slave
See Table 13 and Figure 16. Use these specifications for ADSP-
21160N bus master accesses of a slave’s IOP registers or internal
memory (in multiprocessor memory space). The bus master
must meet these (bus slave) timing requirements.
Table 13. Synchronous Read/Write—Bus Slave
Parameter Min Max Unit
Timing Requirements
t
SADDI
Address, BRST Setup Before CLKIN 5 ns
t
HADDI
Address, BRST Hold After CLKIN 1 ns
t
SRWI
RDx/WRx Setup Before CLKIN 5 ns
t
HRWI
RDx/WRx Hold After CLKIN 1ns
t
SSDATI
Data Setup Before CLKIN 5.5 ns
t
HSDATI
Data Hold After CLKIN 1 ns
Switching Characteristics
t
DDATO
Data Delay After CLKIN 0.25 t
CCLK
+ 9 ns
t
HDATO
Data Hold After CLKIN 1.5 ns
t
DACKC
ACK Delay After CLKIN 10 ns
t
HACKO
ACK Hold After CLKIN 1.5 ns
Figure 16. Synchronous Read/Write—Bus Slave
CLKIN
ADDRESS
ACK
RDx
DATA
(OUT)
WRx
WRITE ACCESS
DATA
(IN)
READ ACCESS
t
SADDI
t
HADDI
t
DACKC
t
HACKO
t
HRWI
t
SRWI
t
DDATO
t
HDATO
t
SRWI
t
HRWI
t
HSDATI
t
SSDATI