Datasheet

–23–REV. 0
ADSP-21160N
Synchronous Read/Write—Bus Master
See Table 12 and Figure 15. Use these specifications for inter-
facing to external memory systems that require CLKIN—relative
timing or for accessing a slave ADSP-21160N (in multiprocessor
memory space). These synchronous switching characteristics are
also valid during asynchronous memory reads and writes except
where noted (see Memory Read–Bus Master on Page 21 and
Memory Write–Bus Master on Page 22). When accessing a slave
ADSP-21160N, these switching characteristics must meet the
slave’s timing requirements for synchronous read/writes (see Syn-
chronous Read/Write–Bus Slave on Page 25). The slave ADSP-
21160N must also meet these (bus master) timing requirements
for data and acknowledge setup and hold times.
Table 12. Synchronous Read/Write—Bus Master
Parameter Min Max Unit
Timing Requirements
t
SSDATI
Data Setup Before CLKIN 5.5 ns
t
HSDATI
Data Hold After CLKIN 1 ns
t
SACKC
ACK Setup Before CLKIN 0.5t
CCLK
+3 ns
t
HACKC
ACK Hold After CLKIN 1 ns
Switching Characteristics
t
DADDO
Address, MSx, BMS, BRST, CIF Delay After CLKIN 10 ns
t
HADDO
Address, MSx, BMS, BRST, CIF Hold After CLKIN 1.5 ns
t
DPGO
PAGE Delay After CLKIN 1.5 11 ns
t
DRDO
RDx High Delay After CLKIN 0.25t
CCLK
– 1 0.25t
CCLK
+9 ns
t
DWRO
WRx High Delay After CLKIN 0.25t
CCLK
– 1 0.25t
CCLK
+9 ns
t
DRWL
RDx/WRx Low Delay After CLKIN 0.25t
CCLK
– 1 0.25t
CCLK
+9 ns
t
DDATO
Data Delay After CLKIN 0.25t
CCLK
+9 ns
t
HDATO
Data Hold After CLKIN 1.5 ns
t
DACKMO
ACK Delay After CLKIN
1
39ns
t
ACKMTR
ACK Disable Before CLKIN
1
–3 ns
t
DCKOO
CLKOUT Delay After CLKIN 0.5 5 ns
t
CKOP
CLKOUT Period t
CK
–1 t
CK
2
+1 ns
t
CKWH
CLKOUT Width High t
CK
/2 – 2 t
CK
/2+2
2
ns
t
CKWL
CLKOUT Width Low t
CK
/2 – 2 t
CK
/2+2
2
ns
1
Applies to broadcast write, master precharge of ACK.
2
Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise. For more information, see the System Design chapter
in the ADSP-2116x SHARC DSP Hardware Reference.