Datasheet
–45–REV. 0
ADSP-21160M
Capacitive Loading
Output delays and holds are based on standard capacitive
loads: 50 pF on all pins (see Figure 31). The delay and hold
specifications given should be derated by a factor of
1.5 ns/50 pF for loads other than the nominal value of
50 pF. Figure 33 and Figure 34 show how output rise time
varies with capacitance. Figure 35 graphically shows how
output delays and holds vary with load capacitance. (Note
that this graph or derating does not apply to output disable
delays; see Output Disable Time on page 44.) The graphs
of Figure 33, Figure 34, and Figure 35 may not be linear
outside the ranges shown.
Environmental Conditions
The ADSP-21160M is tested for performance over the
commercial temperature range, 0°C to 85°C.
Thermal Characteristics
The ADSP-21160M is packaged in a 400-ball Plastic Ball
Grid Array (PBGA). The ADSP-21160M is specified for a
case temperature (T
CASE
). To ensure that the T
CASE
data sheet
specification is not exceeded, a heatsink and/or an air flow
source may be used. Use the center block of ground pins
(PBGA balls: H8–13, J8–13, K8–13, L8–13, M8–13, and
N8–13) to provide thermal pathways to the printed circuit
board’s ground plane. A heatsink should be attached to the
ground plane (as close as possible to the thermal pathways)
with a thermal adhesive.
Figure 31. Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 32. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Figure 33. Typical Output Rise Time (10%–90%,
V
DDEXT
= Max) vs. Load Capacitance
B*
*4"
##
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#
##
B* B*
$4"
B
B
** *
B
B
*B
*B
*B
"
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"
=B'')HBAA
=B))'HB)
Figure 34. Typical Output Rise Time (10%–90%,
V
DDEXT
= Min) vs. Load Capacitance
Figure 35. Typical Output Delay or Hold vs. Load
Capacitance (at Max Case Temperature)
$4"
B
B
** *
B
*B
*B
*B
"
$
+8
"
=B'HB*
=B)AHB
$4"
*B
B
** *
*B
$*B
B
B
##
!
$
+8
=B)**$B)'