Datasheet

ADSP-21160M
–44– REV. 0
Example: Estimate P
EXT
with the following assumptions:
• A system with one bank of external data memory—asyn-
chronous RAM (64-bit)
• Four 64K × 16 RAM chips are used, each with a load of
10 pF
• External data memory writes occur every other cycle, a
rate of 1/(4 t
CK
), with 50% of the pins switching
• The bus cycle time is 40 MHz (t
CK
= 25 ns).
The P
EXT
equation is calculated for each class of pins that
can drive:
A typical power consumption can now be calculated for
these conditions by adding a typical internal power
dissipation:
P
TOTAL
= P
EXT
+ P
INT
+ P
PLL
Where:
• P
EXT
is from Table 30
• P
INT
is I
DDINT
× 2.5V, using the calculation I
DDINT
listed in
Power Dissipation on page 42
• P
PLL
is AI
DD
× 2.5V, using the value for AI
DD
listed in
ABSOLUTE MAXIMUM RATINGS on page 14
Note that the conditions causing a worst-case P
EXT
are
different from those causing a worst-case P
INT
. Maximum
P
INT
cannot occur while 100% of the output pins are
switching from all ones to all zeros. Note also that it is not
common for an application to have 100% or even 50% of
the outputs switching simultaneously.
Test Co nd it i ons
The test conditions for timing parameters appearing in
ADSP-21160M specifications on page 13 include output
disable time, output enable time, and capacitive loading.
Output Disable Time
Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay
from their output high or low voltage. The time for the
voltage on the bus to decay by –V is dependent on the capac-
itive load, C
L
and the load current, I
L
. This decay time can
be approximated by the following equation:
t
DECAY
= (C
L
∆
V)/I
L
The output disable time t
DIS
is the difference between
t
MEASURED
and t
DECAY
as shown in Figure 30. The time t
MEASURED
is the interval from when the reference signal switches to
when the output voltage decays –V from the measured
output high or output low voltage. t
DECAY
is calculated with
test loads C
L
and I
L
, and with –V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have
made a transition from a high impedance state to when they
start driving. The output enable time t
ENA
is the interval from
when a reference signal reaches a high or low voltage level
to when the output has reached a specified high or low trip
point, as shown in the Output Enable/Disable diagram
(Figure 30). If multiple pins (such as the data bus) are
enabled, the measurement value is that of the first pin to
start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular
system, first calculate t
DECAY
using the equation given above.
Choose –V to be the difference between the
ADSP-21160M’s output voltage and the input threshold for
the device requiring the hold time. A typical –V will be 0.4 V.
C
L
is the total bus capacitance (per data line), and I
L
is the
total leakage or three-state current (per data line). The hold
time will be t
DECAY
plus the minimum disable time (i.e.,
t
DATRWH
for the write cycle).
Table 30. External Power Calculations (3.3 V Device)
Pin Type # of Pins % Switching × C × f × VDD
2
= P
EXT
Address 15 50 × 44.7 pF × 12.5 MHz × 10.9 V = 0.046 W
MS0 1 0 × 44.7 pF × 12.5 MHz × 10.9 V = 0.000 W
WRx
2 –× 44.7 pF × 25 MHz × 10.9 V = 0.024 W
Data 64 50 × 14.7 pF × 12.5 MHz × 10.9 V = 0.064 W
CLKOUT 1 –× 4.7 pF × 25 MHz × 10.9 V = 0.001 W
P
EXT
= 0.135 W
Figure 30. Output Enable/Disable
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS
DRIVING
V
OH (MEASURED)
– DV
V
OL (MEASURED)
+ DV
t
MEASURED
V
OH (MEASURED)
V
OL (MEASURED)
2.0V
1.0V
HIGH-IMPEDANCE STATE.
TEST CONDITIONS CAUSE THISVOLTAGE
TO BE APPROXIMATELY 1.5V
OUTPUT STOPS
DRIVING
t
DECAY
t
ENA