Datasheet

–43–REV. 0
ADSP-21160M
The load capacitance should include the processor’s
package capacitance (C
IN
). The switching frequency
includes driving the load high and then back low. Address
and data pins can drive high and low at a maximum rate of
1/(2t
CK
). The write strobe can switch every cycle at a
frequency of 1/t
CK
. Select pins switch at 1/(2t
CK
), but selects
can switch on each cycle.
Table 29. ADSP-21160M Operation Types vs. Input Current
Operation Peak Activity
1
High Activity
1
Low Activity
1
Instruction Type Multifunction Multifunction Single Function
Instruction Fetch Cache Internal Memory Internal Memory
Core Memory Access
2
2 per t
CK
cycle
(DMⴛ64 and PMⴛ64)
1 per t
CK
cycle
(DMⴛ64)
None
Internal Memory DMA 1 per 2 t
CCLK
cycles 1 per 2 t
CCLK
cycles None
External Memory DMA 1 per external port cycle (ⴛ64) 1 per external port cycle (ⴛ64) None
Data bit pattern for core
memory access and DMA
Wor st cas e Random N/A
1
Peak Activity=I
DDINPEAK
, High Activity=I
DDINHIGH
, and Low Activity=I
DDINLOW
. The state of the PEYEN bit (SIMD versus SISD mode) does not influence
these calculations.
2
These assume a 2:1 core clock ratio. For more information on ratios and clocks (t
CK
and t
CCLK
), see the timing ratio definitions on page 15.