Datasheet

–41–REV. 0
ADSP-21160M
JTAG Test Access Port and Emulation
Table 28. JTAG Test Access Port and Emulation
Parameter Min Max Unit
Timing Requirements:
t
TCK
TCK Period t
CK
ns
t
STAP
TDI, TMS Setup Before TCK High 5 ns
t
HTAP
TDI, TMS Hold After TCK High 6 ns
t
SSYS
System Inputs Setup Before TCK Low
1
1
System Inputs = DATA63–0, ADDR31–0, RDx, WRx, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0,
PA
, BRST, DR0, DR1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN,
RESET
.
7ns
t
HSYS
System Inputs Hold After TCK Low
1
18 ns
t
TRSTW
TRST Pulsewidth 4t
CK
ns
Switching Characteristics:
t
DTDO
TDO Delay from TCK Low 13 ns
t
DSYS
System Outputs Delay After TCK Low
2
2
System Outputs = DATA63–0, ADDR31–0, MS3–0, RDx, WRx, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF,
FLAG3–0, TIMEXP, DT0, DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS
.
30 ns
Figure 28. IEEE 11499.1 JTAG Test Access Port





#

##
,

,

,
!
,

,

,
!
,
