Datasheet

–37–REV. 0
ADSP-21160M
Serial Ports
To determine whether communication is possible between
two devices at clock speed n, the following specifications
must be confirmed: 1) frame sync delay and frame sync
setup and hold, 2) data delay and data setup and hold, and
3) SCLK width.
Table 21. Serial Ports—External Clock
Parameter Min Max Unit
Timing Requirements:
t
SFSE
TFS/RFS Setup Before TCLK/RCLK
1
3.5 ns
t
HFSE
TFS/RFS Hold After TCLK/RCLK
1,2
4ns
t
SDRE
Receive Data Setup Before RCLK
1
1.5 ns
t
HDRE
Receive Data Hold After RCLK
1
4ns
t
SCLKW
TCLK/RCLK Width 14 ns
t
SCLK
TCLK/RCLK Period 2t
CCLK
ns
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 22. Serial Ports—Internal Clock
Parameter Min Max Unit
Timing Requirements:
t
SFSI
TFS Setup Before TCLK
1
; RFS Setup Before RCLK
1
8ns
t
HFSI
TFS/RFS Hold After TCLK/RCLK
1,2
1ns
t
SDRI
Receive Data Setup Before RCLK
1
6.5 ns
t
HDRI
Receive Data Hold After RCLK
1
3ns
1
Referenced to sample edge.
2
RFS hold after RCK when MCE = 1, MFD = 0 is 0 ns minimum from drive edge. TFS hold after TCK for late external TFS is 0 ns minimum from drive edge.
Table 23. Serial Ports—External or Internal Clock
Parameter Min Max Unit
Switching Characteristics:
t
DFSE
RFS Delay After RCLK (Internally Generated RFS)
1
13 ns
t
HOFSE
RFS Hold After RCLK (Internally Generated RFS)
1
3ns
1
Referenced to drive edge.
Table 24. Serial Ports—External Clock
Parameter Min Max Unit
Switching Characteristics:
t
DFSE
TFS Delay After TCLK (Internally Generated TFS)
1
13 ns
t
HOFSE
TFS Hold After TCLK (Internally Generated TFS)
1
3ns
t
DDTE
Transmit Data Delay After TCLK
1
16 ns
t
HDTE
Transmit Data Hold After TCLK
1
0ns
1
Referenced to drive edge.
Table 25. Serial Ports—Internal Clock
Parameter Min Max Unit
Switching Characteristics:
t
DFSI
TFS Delay After TCLK (Internally Generated TFS)
1
4.5 ns
t
HOFSI
TFS Hold After TCLK (Internally Generated TFS)
1
–1.5 ns