Datasheet

ADSP-21160M
–30– REV. 0
Three-State Timing—Bus Master and Bus Slave
These specifications show how the memory interface is
disabled (stops driving) or enabled (resumes driving)
relative to CLKIN and the SBTS
pin. This timing is appli-
cable to bus master transition cycles (BTC) and host
transition cycles (HTC) as well as the SBTS
pin.
Table 16. Three-State Timing—Bus Slave, HBR, SBTS
Parameter Min Max Unit
Timing Requirements:
t
STSCK
SBTS Setup Before CLKIN 6ns
t
HTSCK
SBTS Hold After CLKIN 1ns
Switching Characteristics:
t
MIENA
Address/Select Enable After CLKIN 1.5 9 ns
t
MIENS
Strobes Enable After CLKIN
1
1.5 9 ns
t
MIENHG
HBG Enable After CLKIN 1.5 9 ns
t
MITRA
Address/Select Disable After CLKIN 0.25t
CCLK
– 1 0.25t
CCLK
+4 ns
t
MITRS
Strobes Disable After CLKIN
1
0.25t
CCLK
– 4 0.25t
CCLK
ns
t
MITRHG
HBG Disable After CLKIN 3.5 8 ns
t
DATEN
Data Enable After CLKIN
2
1.5 10 ns
t
DATTR
Data Disable After CLKIN
2
1.5 5 ns
t
ACKEN
ACK Enable After CLKIN
2
1.5 9 ns
t
ACKTR
ACK Disable After CLKIN
2
1.5 5 ns
t
CDCEN
CLKOUT Enable After CLKIN 1.5 9 ns
t
CDCTR
CLKOUT Disable After CLKIN t
CCLK
– 3t
CCLK
+1 ns
t
MTRHBG
Memory Interface Disable Before HBG
Low
3
t
CK
– 6t
CK
+2 ns
t
MENHBG
Memory Interface Enable After HBG
High
3
t
CK
– 5t
CK
+5 ns
1
Strobes = RDx, WRx, DMAGx.
2
In addition to bus master transition cycles, these specs also apply to bus master and bus slave synchronous read/write.
3
Memory Interface = Address, RDx, WRx, MSx, PAGE, DMAGx, and BMS (in EPROM boot mode).