Datasheet

ADSP-21160M
–28– REV. 0
Asynchronous Read/Write—Host to ADSP-21160M
Use these specifications (Table 14 and Table 15) for asyn-
chronous host processor accesses of an ADSP-21160M,
after the host has asserted CS
and HBR (low). After HBG
is returned by the ADSP-21160M, the host can drive the
RDx
and WRx pins to access the ADSP-21160M’s internal
memory or IOP registers. HBR
and HBG are assumed low
for this timing
Table 14. Read Cycle
Parameter Min Max Unit
Timing Requirements:
t
SADRDL
Address Setup/CS Low Before RDx Low 0 ns
t
HADRDH
Address Hold/CS Hold Low After RDx 2ns
t
WRWH
RDx/WRx High Width 5ns
t
DRDHRDY
RDx High Delay After REDY (O/D) Disable 0ns
t
DRDHRDY
RDx High Delay After REDY (A/D) Disable 0ns
Switching Characteristics:
t
SDATRDY
Data Valid Before REDY Disable from Low 2 ns
t
DRDYRDL
REDY (O/D) or (A/D) Low Delay After RDx Low 10 ns
t
RDYPRD
REDY (O/D) or (A/D) Low Pulsewidth for Read t
CK
ns
t
HDARWH
Data Disable After RDx High 26ns
Figure 20. Read Cycle (Asynchronous Read—Host to ADSP-21160M)
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