Datasheet

ADSP-21160M
–26– REV. 0
Multiprocessor Bus Request and Host Bus Request
Use these specifications for passing of bus mastership
between multiprocessing ADSP-21160Ms (BRx
) or a host
processor (HBR
, HBG).
Table 13. Multiprocessor Bus Request and Host Bus Request
Parameter Min Max Unit
Timing Requirements:
t
HBGRCSV
HBG Low to RDx/WRx/CS Valid 19 ns
t
SHBRI
HBR Setup Before CLKIN
1
6ns
t
HHBRI
HBR Hold After CLKIN
1
1ns
t
SHBGI
HBG Setup Before CLK/=’]IN 6ns
t
HHBGI
HBG Hold After CLKIN High 1ns
t
SBRI
BRx, PA Setup Before CLKIN 9ns
t
HBRI
BRx, PA Hold After CLKIN High 1ns
t
SPAI
PA Setup Before CLKIN 9ns
t
HPAI
PA Hold After CLKIN High 1ns
t
SRPBAI
RPBA Setup Before CLKIN 6 ns
t
HRPBAI
RPBA Hold After CLKIN 2 ns
Switching Characteristics:
t
DHBGO
HBG Delay After CLKIN 7ns
t
HHBGO
HBG Hold After CLKIN 2ns
t
DBRO
BRx Delay After CLKIN 8ns
t
HBRO
BRx Hold After CLKIN 1.5 ns
t
DPASO
PA Delay After CLKIN, Slave 8ns
t
TRPAS
PA Disable After CLKIN, Slave 1.5 ns
t
DPAMO
PA Delay After CLKIN, Master 0.25t
CCLK
+9 ns
t
PATR
PA Disable Before CLKIN, Master 0.25t
CCLK
– 5ns
t
DRDYCS
REDY (O/D) or (A/D) Low from CS and HBR Low
2
0.5t
CK
ns
t
TRDYHG
REDY (O/D) Disable or REDY (A/D) High from HBG
2
t
CK
+25 ns
t
ARDYTR
REDY (A/D) Disable from CS or HBR High
2
11 ns
1
Only required for recognition in the current cycle.
2
(O/D) = open drain, (A/D) = active drive.