Datasheet

ADSP-21160M
–22– REV. 0
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for
accessing a slave ADSP-21160M (in multiprocessor
memory space). These synchronous switching characteris-
tics are also valid during asynchronous memory reads and
writes except where noted (see Memory Read—Bus Master
on page 19 and Memory Write—Bus Master on page 20).
When accessing a slave ADSP-21160M, these switching
characteristics must meet the slave’s timing requirements
for synchronous read/writes (see Synchronous
Read/Write—Bus Slave on page 24). The slave
ADSP-21160M must also meet these (bus master) timing
requirements for data and acknowledge setup and hold
times.
Table 11. Synchronous Read/Write—Bus Master
Parameter Min Max Unit
Timing Requirements:
t
SSDATI
Data Setup Before CLKIN
1
5.5 ns
t
HSDATI
Data Hold After CLKIN
1
1ns
t
SACKC
ACK Setup Before CLKIN
1
0.5t
CCLK
+3 ns
t
HACKC
ACK Hold After CLKIN
1
1ns
Switching Characteristics:
t
DADDO
Address, MSx, BMS, BRST, CIF Delay After CLKIN 10 ns
t
HADDO
Address, MSx, BMS, BRST, CIF Hold After CLKIN 1.5 ns
t
DPGO
PAGE Delay After CLKIN 1.5 11 ns
t
DRDO
RDx High Delay After CLKIN
1
0.25t
CCLK
– 1 0.25t
CCLK
+9 ns
t
DWRO
WRx High Delay After CLKIN
1
0.25t
CCLK
– 1 0.25t
CCLK
+9 ns
t
DRWL
RDx/WRx Low Delay After CLKIN 0.25t
CCLK
– 1 0.25t
CCLK
+9 ns
t
DDATO
Data Delay After CLKIN 12.5 ns
t
HDATO
Data Hold After CLKIN 1.5 ns
t
DACKMO
ACK Delay After CLKIN
2
0.25t
CCLK
+3 0.25t
CCLK
+9 ns
t
ACKMTR
ACK Disable Before CLKIN
2
0.25t
CCLK
– 3ns
t
DCKOO
CLKOUT Delay After CLKIN 25ns
t
CKOP
CLKOUT Period t
CK
– 1t
CK
3
+1 ns
t
CKWH
CLKOUT Width High t
CK
/2 – 2t
CK
/2+2
3
ns
t
CKWL
CLKOUT Width Low t
CK
/2 – 2t
CK
/2+2
3
ns
1
Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to synchronous access mode.
2
Applies to broadcast write, master precharge of ACK.
3
Applies only when the DSP drives a bus operation; CLKOUT held inactive or three-state otherwise, For more information, see the System Design chapter
in the ADSP-2116x SHARC DSP Hardware Reference.