Datasheet

–19–REV. 0
ADSP-21160M
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to
memories (and memory-mapped peripherals) without
reference to CLKIN. These specifications apply when the
ADSP-21160M is the bus master accessing external
memory space in asynchronous access mode. Note that
timing for ACK, DATA, RDx
, WRx, and DMAG strobe
timing parameters only applies to asynchronous access
mode.
Table 9. Memory Read—Bus Master
Parameter Min Max Unit
Timing Requirements:
t
DAD
Address, CIF, Selects Delay to Data
Valid
1,2
t
CK
– 0.25t
CCLK
– 11+W ns
t
DRLD
RDx Low to Data Valid
1,3
0.75t
CK
–11+W ns
t
HDA
Data Hold from Address, Selects
4
0ns
t
SDS
Data Setup to RDx High
1
8ns
t
HDRH
Data Hold from RDx High
3,4
1ns
t
DAAK
ACK Delay from Address, Selects
2,5
t
CK
– 0.5t
CCLK
– 12+W ns
t
DSAK
ACK Delay from RDx Low
3,5
t
CK
– 0.75t
CCLK
– 11+W ns
t
SAKC
ACK Setup to CLKIN
3,5
0.5t
CCLK
+3 ns
t
HAKC
ACK Hold After CLKIN
3
1ns
Switching Characteristics:
t
DRHA
Address, CIF, Selects Hold After RDx
High
3
0.25t
CCLK
– 1+H ns
t
DARL
Address, CIF, Selects to RDx Low
2
0.25t
CCLK
– 3ns
t
RW
RDx Pulse width
3
t
CK
– 0.5t
CCLK
– 1+W ns
t
RWR
RDx High to WRx, RDx, DMAGx Low
3
0.5t
CCLK
– 1+HI ns
W = (number of wait states specified in WAIT register) ⴛ t
CK
.
HI = t
CK
(if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = t
CK
(if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
1
Data Delay/Setup: User must meet t
DAD
, t
DRLD
, or t
SDS.
2
The falling edge of MSx, BMS is referenced.
3
Note that timing for ACK, DATA, RDx, WRx, and DMAG strobe timing parameters only applies to asynchronous access mode.
4
Data Hold: User must meet t
HDA
or t
HDRH
in asynchronous access mode. See Example System Hold Time Calculation on page 44 for the calculation of
hold times given capacitive and dc loads.
5
ACK Delay/Setup: User must meet t
DAAK
, t
DSAK
, or t
SAKC
for deassertion of ACK (Low), all three specifications must be met for assertion of ACK (High).
Figure 15. Memory Read—Bus Master
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