Datasheet

ADSP-21160M
–16– REV. 0
Clock Input
Reset
Table 4. Clock Input
Parameter
80 MHz
Unit
Min Max
Timing Requirements:
t
CK
CLKIN Period 25 80 ns
t
CKL
CLKIN Width Low 10.5 40 ns
t
CKH
CLKIN Width High 10.5 40 ns
t
CKRF
CLKIN Rise/Fall (0.4V–2.0V) 3 ns
Figure 10. Clock Input
Table 5. Reset
Parameter Min Max Unit
Timing Requirements:
t
WRST
RESET Pulsewidth Low
1
1
Applies after the power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 100 ms while RESET is
low, assuming stable VDD and CLKIN (not including start-up time of external clock oscillator).
4t
CK
ns
t
SRST
RESET Setup Before CLKIN High
2
2
Only required if multiple ADSP-21160Ms must come out of reset synchronous to CLKIN with program counters (PC) equal. Not required for multiple
ADSP-21160Ms communicating over the shared bus (through the external port), because the bus arbitration logic automatically synchronizes itself
after reset.
8ns
Figure 11. Reset
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