Datasheet
–11 –REV. 0
ADSP-21160M
DMAG2 O/T DMA Grant 2 (DMA Channel 12). Asserted by ADSP-21160M to indicate that the
requested DMA starts on the next cycle. Driven by bus master only.
BR6–1
I/O/S Multiprocessing Bus Requests. Used by multiprocessing ADSP-21160Ms to arbitrate
for bus mastership. An ADSP-21160M only drives its own BRx
line (corresponding to
the value of its ID2–0 inputs) and monitors all others. In a multiprocessor system with
less than six ADSP-21160Ms, the unused BRx
pins should be pulled high; the
processor’s own BRx
line must not be pulled high or low because it is an output.
RPBA I/S Rotating Priority Bus Arbitration Select. When RPBA is high, rotating priority for
multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected.
This signal is a system configuration selection which must be set to the same value on
every ADSP-21160M. If the value of RPBA is changed during system operation, it must
be changed in the same CLKIN cycle on every ADSP-21160M.
PA
I/O/T Priority Access. Asserting its PA pin allows an ADSP-21160M bus slave to interrupt
background DMA transfers and gain access to the external bus. PA
is connected to all
ADSP-21160Ms in the system. If access priority is not required in a system, the PA
pin
should be left unconnected.
DTx O Data Transmit (Serial Ports 0, 1). Each DT pin has a 50 k
Ω
internal pull-up resistor.
DRx I Data Receive (Serial Ports 0, 1). Each DR pin has a 50 k
Ω
internal pull-up resistor.
TCLKx I/O Transmit Clock (Serial Ports 0, 1). Each TCLK pin has a 50 k
Ω
internal
pull-up resistor.
RCLKx I/O Receive Clock (Serial Ports 0, 1). Each RCLK pin has a 50 k
Ω
internal pull-up resistor.
TFSx I/O Transmit Frame Sync (Serial Ports 0, 1).
RFSx I/O Receive Frame Sync (Serial Ports 0, 1).
LxDAT7–0 I/O Link Port Data (Link Ports 0–5). Each LxDAT pin has a 50 k
Ω
internal pull-down
resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1 register.
LxCLK I/O Link Port Clock (Link Ports 0–5). Each LxCLK pin has a 50 k
Ω
internal pull-down
resistor that is enabled or disabled by the LPDRD bit of the LCTL0–1register.
LxACK I/O Link Port Acknowledge (Link Ports 0–5). Each LxACK pin has a 50 k
Ω
internal
pull-down resistor that is enabled or disabled by the LPDRD bit of the LCOM register.
EBOOT I EPROM Boot Select. For a description of how this pin operates, see Table 3. This
signal is a system configuration selection that should be hardwired.
LBOOT I Link Boot. For a description of how this pin operates, see Table 3. This signal is a
system configuration selection that should be hardwired.
BMS
I/O/T Boot Memory Select. Serves as an output or input as selected with the EBOOT and
LBOOT pins; see Table 3. This input is a system configuration selection that should
be hardwired.
CLKIN I Local Clock In. CLKIN is the ADSP-21160M clock input. The ADSP-21160M
external port cycles at the frequency of CLKIN. The instruction cycle rate is a multiple
of the CLKIN frequency; it is programmable at power-up. CLKIN may not be halted,
changed, or operated below the specified frequency.
CLK_CFG3–0 I Core/CLKIN Ratio Control. ADSP-21160M core clock (instruction cycle) rate is equal
to n ⴛ CLKIN where n is user-selectable to 2, 3, or 4, using the CLK_CFG3–0 inputs.
For clock configuration definitions, see the RESET
& CLKIN section of the System
Design chapter of the ADSP-21160 SHARC DSP Hardware Reference manual.
CLKOUT O/T Local Clock Out. CLKOUT is driven at the CLKIN frequency by the current bus
master. This output is three-stated when the ADSP-21160M is not the bus master, or
when the host controls the bus (HBG
asserted). A keeper latch on the DSP’s CLKOUT
pin maintains the output at the level it was last driven (only enabled on the
ADSP-21160M with ID2–0 = 00x).
RESET
I/A Processor Reset. Resets the ADSP-21160M to a known state and begins execution at
the program memory location specified by the hardware reset vector address. The
RESET
input must be asserted (low) at power-up.
Table 2. Pin Function Descriptions (Continued)
Pin Type Function