Datasheet

REV. C
ADSP-21065L
–37–
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
50 pF on all pins. The delay and hold specifications given
should be derated by a factor of l.8 ns/50 pF for loads other
than the nominal value of 50 pF. Figure 28 and Figure 29 show
how output rise time varies with capacitance. Figure 30 shows
graphically how output delays and hold vary with load capaci-
tance. (Note that this graph or derating does not apply to output
disable delays; see the previous section Output Disable time
under Test Conditions.) The graphs of Figure 28, Figure 29,
and Figure 30 may not be linear outside the ranges shown.
LOAD CAPACITANCE – pF
0
0 20020
RISE AND FALL TIMES – ns
40 60 80 100 120 140 160 180
2
RISE TIME
FALL TIME
4
6
8
10
12
14
16
18
Figure 28. Typical Rise and Fall Time (10%–90% V
DD
)
LOAD CAPACITANCE – pF
8.0
4.0
0
020020
RISE AND FALL TIMES – ns
40 60 80 100 120 140 160 180
7.0
6.0
2.0
1.0
5.0
3.0
RISE TIME
FALL TIME
Figure 29. Typical Rise and Fall Time (0.8 V–2.0 V)
LOAD CAPACITANCE – pF
OUTPUT DELAY OR HOLD – ns
5
–2
0 14020 40 60 80 100 120
4
3
2
1
0
–1
160 180 200
6
Figure 30. Typical Output Delay or Hold